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Socket 939 Discussion Thread


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Thanks everyone for your help. I got all the other 3dmark products installed and they all ran correctly. I have screenshots and will post them after I get my prime95 rerun with both cores finished.

 

Sorry for asking so many why questions. Just trying to understand why something is relevant. Guess that is what happens when you are an engineer. Thanks again Lowboy, CPDMF, Flowerking, Praz and Oldguy!

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Junfan

In case you haven't seen it yet here is the link for the proper way of posting in the OCDB. Post #3 has the 939 database template attached for download. Just paste your data over the existing info.

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Thank you I have the template now.

 

I have been reading all day and am now at the following settings. Everything has run successfully so far except prime95 dual core which I will start when I go to bed.

 

 

Genie BIOS Settings:

 

FSB Bus Frequency............................. - 240

LDT/FSB Frequency Ratio....................... - X4

CPU/FSB Frequency Ratio....................... - X11

PCI eXpress Frequency......................... - 100Mhz

 

CPU VID StartUp Value......................... - Startup

 

CPU VID Control............................... - 1.350

CPU VID Special Control....................... - X 112.0%

LDT Voltage Control........................... - 1.30v

Chip Set Voltage Control...................... - 1.59v

DRAM Voltage Control.......................... - 2.74v

 

DRAM Configuration Settings:

 

DRAM Frequency Set............................ - 200=RAM/FSB:01/01

Command Per Clock (CPC)....................... - Auto

CAS Latency Control (Tcl)..................... - 2.5

RAS# to CAS# delay (Trcd)..................... - 3 Bus Clocks

Min RAS# active time (Tras)................... - 6 Bus Clocks

Row precharge time (Trp)...................... - 3 Bus Clocks

Row Cycle time (Trc).......................... - 7 Bus Clocks

Row refresh cyc time (Trfc)................... - Auto

Row to Row delay (Trrd)....................... - 02 Bus Clocks

Write recovery time (Twr)..................... - 02 Bus Clocks

Write to Read delay (Twtr).................... - 02 Bus Clocks

Read to Write delay (Trwt).................... - 03 Bus Clocks

Refresh Period (Tref)......................... - 3120 Cycles

DRAM Bank Interleave.......................... - Enabled

 

Thank god for DFI Street I am finally starting to understand. OCing this thing was very scary at first. So many damn settings. HAHA.

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Alright got my sig fixed and got all my stuff ready to submit. My machine ran great. Now how do I submit this for the db so I do not do anything stupid again.

 

Also, the Prime95 test ran on my sons machine for 7hours58mins with 0 errors. Can I still submit his or do I have to rerun to get the last 2 mins?

 

Thanks!

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New entry in ocdb.This is my second enrty with my 146,but with new ram.G.Skill,HZ.What a diffrence with this ram compared to my G.Skill 4800.Lower voltage due to the uccc memory.My Trrd,Twr,Twtr & the Trwt ,i was able to tighten them up a bit as the Tref also.Running this ram took me right up to 3000.7 Mhz with almost no issues.I think its time to go dual core.

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Alright got my sig fixed and got all my stuff ready to submit. My machine ran great. Now how do I submit this for the db so I do not do anything stupid again.

 

Also, the Prime95 test ran on my sons machine for 7hours58mins with 0 errors. Can I still submit his or do I have to rerun to get the last 2 mins?

 

Thanks!

 

All entries have to be 8 hours minimum...

 

When filling out the template, make sure you copy and paste into a post and use the preview to make sure it is good, rather than trying to go back and forth fixining it before the mods delete it. Just look at a few posts and make sure yours looks the same before you hit the submit button...

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