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"in Your Face Flanders!" (5.1ghz Ocdb Entry)


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The actual set Vcore is 1.566v, what you are seeing at 1.55 is a small amount of Vdroop. Compared to a lot of what i have been seeing on different forums, my E8500 needs a shed load of Vcore to get where it is. But then again, mine is stable and to be honest, i doubt very much whether a lot of what i have seen around is stable at all. I certainly hav'nt seen a lot of proof anyway, just a bucket load of Cpuz suicide shots.

 

Nice. How much farther are you going to push it? I imagine the phase unit can handle much more yet, should you decide to aim a bit higher. I'm sure 5G's would be a tough, tough mark to hit stable but it'd really entertain me to see you try! :angel:

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Nice. How much farther are you going to push it? I imagine the phase unit can handle much more yet, should you decide to aim a bit higher. I'm sure 5G's would be a tough, tough mark to hit stable but it'd really entertain me to see you try! :angel:

 

Thank's dan, 5ghz :eek: i would love to think that this chip would do it, but the reality is George Wyaaaa is more likely to be re-elected than this reach 5ghz :nod:. However, i do think that 4.7ghz is a target that could be achievable. I know already that 4.65ghz is ok, just got to find the right GTL's for the increase in fsb.

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At the speeds you are at now the percentage of GTLREF is pretty much constant. If you can get a hold of a meter or scope that is accurate to at least three decimal places measure your current values. Convert those measurement to a percentage of VTT to at least 2 decimal places. Use those percentages as you increase VTT. Then the only variable remaining is the relationship of VTT to NB voltage.

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Yes you'r right on it being constant John. I know that because when i tried it at 4.65 last week, the "ball breaker" was VTT to NB voltage. But what i did'nt try at that time was an increase in Clockgen voltage, which is what i'm trying at the moment. It looks promising, but it "ain't done until it's done" :)

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Well, clockgen voltage was a complete waste of time. All it seems to do for me at the end of the day is make the system unstable. Back to some hard graft then, and see if i can find another route to 4.65ghz.

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Just an update as to where the clock is at the moment. I have had a few probs with consistancy at 4.65. I had the same thing at 4.6 to start with, and the prob was fine delay. So i went on the same assumption again, and i was right. It looks like a change of strap has happened between 512fsb and 517fsb. It took a bit of time to find the right fine delay settings, but i think i have got them right now.

 

Anyway, the screenie below is Orthosing away as i type. If it goes the full distance, i'll post the result up latter today. An OCDB entry for it will have to wait untill next weekend though, because i'll be away all week.

 

normal_4_65-2.JPG

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  • 3 weeks later...

An update on the goings on at Kit's place. The screenie below is where i've got to so far with the new E8500. As you can see it's a better clocker than the first one. I have already got it well stable at 4.7ghz with no problems at all. The run below will be left to go all night, then i'll run "blend" tommorow. If all goes Ok, then................well, it would be criminal not to try for 4.8ghz................would'nt it :D

 

normal_4_75-Test.JPG

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Graham, what core temps are you seeing in that screenshot?

 

-61c on the Evap and Speedfan is showing the CPU at -21c. I must admit John, the DFI and this E8500 are flying................and i'm lovin it :nod:

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