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cegras

Topped out on 3800 X2 ..?

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Hey;

 

I won't be able to try these things out until after I replace my 3850. It's been causing instability for me in games and as a result I'm backing off the overclock just slightly to see if I can stabilize things.

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running my first x2 3800+ @ 2.7 1.5ghz, vdroop to 1.55

 

and now my 2nd X2 @ 2.74 1.45ghz, vdroop to 1.5

 

(somehow those are the max voltages my mobo gives out)

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running my first x2 3800+ @ 2.7 1.5ghz, vdroop to 1.55

 

and now my 2nd X2 @ 2.74 1.45ghz, vdroop to 1.5

 

(somehow those are the max voltages my mobo gives out)

 

you mind listing your current bios settings? :D

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I've found that if it's hanging at the verifying DMI pool data, it's usually a problem with the memory.

 

I had a horrible time getting my memory and dividers working nicely, the key settings seem to be the DRAM drive strength and DRAM data drive strength.

 

If interested, here are my 24/7 stable settings for the 3800+ in my sig:

 

[b]Genie BIOS Settings:[/b]

[color=red]

FSB Bus Frequency  -  280

LDT/FSB Frequency Ratio  -  4x

CPU/FSB Frequency Ratio  -  10x

PCI eXpress Frequency  -  100Mhz



CPU VID StartUp Value  -  1.35v



CPU VID Control  -  1.350v

CPU VID Special Control  -  Auto

LDT Voltage Control  -  1.20v 

Chip Set Voltage Control  -  1.50v

DRAM Voltage Control  -  2.50v[/color]



[b]DRAM Configuration Settings:[/b]

[color=red]

DRAM Frequency Set  -  180=RAM/FSB:09/10

Command Per Clock (CPC)  -  2T

CAS Latency Control (Tcl)  -  3T

RAS# to CAS# delay (Trcd)  -  03 Bus Clocks

Min RAS# active time (Tras)  -  08 Bus Clocks

Row precharge time (Trp)  -  02 Bus Clocks

Row Cycle time (Trc)  -  10 Bus Clocks

Row refresh cyc time (Trfc)  -  12 Bus Clocks

Row to Row delay (Trrd)  -  02 Bus Clocks

Write recovery time (Twr)  -  02 Bus Clocks

Write to Read delay (Twtr)  -  01 Bus Clock

Read to Write delay (Trwt)  -  03 Bus Clocks

Refresh Period (Tref)  -  2560 Cycles

Write CAS Latency (Twcl)  -  1t

DRAM Bank Interleave  -  Enabled



DQS Skew Control  -  Disabled

DQS Skew Value   -  0

DRAM Drive Strength  -  Weak 4

DRAM Data Drive Strength  -  1 (50% reduction)

Max Async Latency  -  8.0 Nano Seconds

Read Preamble Time  -  6.0 Nano Seconds

IdleCycle Limit  -  16 Cycles

Dynamic Counter  -  Enabled

R/W Queue Bypass  -  16 x

Bypass Max  -  07 x

32 Byte Granularity  -  Disable(4 Bursts)

[/color]

 

edit: Fixed a couple settings. (Drive Strength and tref)

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its sad that i have a manchester core. it seems that the Toledo's are a better clocker. should've taken the toledo when i order mine..damn it, but idk what hit me in the head, that; at that moment when i was ordering my 3800 x2, i thought to myself the manchester was a better revision. arg~ but i believe the toledo's run a bit hotter than the manchester's?

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It's more of a luck-of-the-draw than anything. You may get a dud, you may get a star. It's not like you could've told when you bought the chip.

 

My Toledo runs pretty toasty as well, but that's probably due to poor airflow in my case, which I'm going to fix pretty soon. I got mine to 2.7GHz at stock volts.

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Zellig: my RAM is actually running LOWER than 200 Mhz DDR when I tried for above 270. (used a 7/10 divider). The BE-5 chips top out at 222 mhz so if I want to go higher than 2.66 I need to use a divider.

 

I have 2.75 stable but it just won't budge above that.

 

: )

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Zellig: my RAM is actually running LOWER than 200 Mhz DDR when I tried for above 270. (used a 7/10 divider). The BE-5 chips top out at 222 mhz so if I want to go higher than 2.66 I need to use a divider.

 

I have 2.75 stable but it just won't budge above that.

 

: )

 

Yeah, I wasn't talking about ram speed specifically, when the "FSB Bus Frequency" is high, dividers will "randomly" not work, even if the speed the memory is running at should be alright.

 

Before playing heavily with the secondary ram settings, the ONLY dividers I could get working properly at high FSB settings were 1:1 and 1:2.

 

 

Might not be worth the effort of going past 2.75 if you're happy with that though, my chip does 2.8 with under stock voltage, but I figured that the extra performance from another .1 or .2 GHz wasn't worth my time trying to get the ram dividers working happily.

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Yeah, I wasn't talking about ram speed specifically, when the "FSB Bus Frequency" is high, dividers will "randomly" not work, even if the speed the memory is running at should be alright.

 

I never had any problems with RAM dividers not working randomly or otherwise. My resulting RAM frequency was always exactly what Gogar's or A64MemFreq calculated it out to be.

 

Can you expound on that a little bit?

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I never had any problems with RAM dividers not working randomly or otherwise. My resulting RAM frequency was always exactly what Gogar's or A64MemFreq calculated it out to be.

 

Can you expound on that a little bit?

 

I meant that with certain dividers, everything will hang or reboot after "verifying dmi pool data".

 

It's not random, as in actually random, I just don't happen to know exactly what settings cause certain dividers to work or not work at different speeds.

 

All my testing was done with 4gb of ram on this board, which may have affected what worked, and what didn't.

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