Guest nomad Posted September 8, 2005 Posted September 8, 2005 I am putting a system together for a friend and he wanted Tight timings on his RAM since he is getting an FX. I am running a 13 multi and want 2-2-2-6 or 7 timings. I am running Geil Ultra-X and it is TCCD for sure, but I cant get it stable. I am tryin this on a Ultra-D with a Modstream 520 P/S Here is what I have so far. .. DRAM Configuration Settings: DRAM Frequency Set - 200 (DRAM/FSB:1/01) Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2 RAS# to CAS# delay (Trcd) - 02 Bus Clocks Min RAS# active time (Tras) - 07 Bus Clocks Row precharge time (Trp) - 02 Bus Clocks Row Cycle time (Trc) - 08 Bus Clocks Row refresh cyc time (Trfc) - 16 Bus Clocks Row to Row delay (Trrd) - 03 Bus Clocks Write recovery time (Twr) - 02 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trwt) - 03 Bus Clocks Refresh Period (Tref) - 3120 Cycles Write CAS Latency (Twcl) - Auto DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - Level 7 DRAM Data Drive Strength - Level2 Max Async Latency - 07.0 nano seconds Read Preamble Time - Auto IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(4 Bursts) @2.7-2.8v Anybody have any ideas?:confused: Thanks Share this post Link to post Share on other sites More sharing options...
TheFlowerKing Posted September 8, 2005 Posted September 8, 2005 What happens with everything set on auto? Share this post Link to post Share on other sites More sharing options...
Guest nomad Posted September 8, 2005 Posted September 8, 2005 I pass Memtest fine but then I get to Windows and fail SuperPi really quick during a 32M but make it through 1M. I am beginning to think they are buggered. I will try 7-02 BT and one at a time and see for sure. I know it is not the CPU cuz I had it at 2.65 13hours prime with my TCCD. Also had it to 2.7 under water. Anybody have more timings to try?? Thnx Share this post Link to post Share on other sites More sharing options...
smolt Posted September 8, 2005 Posted September 8, 2005 Why do you have such a big span between trc and trfc from what i read trfc should run two above trc ? and have you tryed twtr 1 trwt 2 ? Share this post Link to post Share on other sites More sharing options...
Guest nomad Posted September 8, 2005 Posted September 8, 2005 No worries. Damaged the naked core. Goes in the garbage... :sad: Looks like the memcontroler got a chip in it and now it is history. I guess there is always a first for everything. No spending money this month. Share this post Link to post Share on other sites More sharing options...
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