tictac

thanks mate... logging out...

still can't find the log out botton.. i'm leaving my nickname on... PM me if you know how to logout from this forum.. See ya.. take care tictac

hey... where is the log out botton?? i lost on my way out.... my bad

The PCI ROM version: Make sure the device and vendor id match your device id the id i post in the source code is nForce2 NIC ID... you need to change that PCI device wont beuseable if you swap the rom with the compile rom But your code will be set... cbrom biosname.bin /pci patch.bin thanks, tictac ;--------------------------------------------------------------------------------------------------- ; AMD Athlon 64 DDR PCI ROM Patcher Rev 3.0 simple ;--------------------------------------------------------------------------------------------------- ; ; Source code writen by tictac ; Website : z6.invisionfree.com/tictac ; Note : Free to be distribute/mod , Use it at your own risk ; ;--------------------------------------------------------------------------------------------------- ;------------------------------CODE DEFINITION------------------------------------------------------ ;--------------------------------------------------------------------------------------------------- use16 ; 16bit mode address equ 0CF8h ; address port data equ 0CFCh ; data port dtl_add equ 08000C288h ; DRAM Timing Low address dth_add equ 08000C28Ch ; DRAM Timing High address dcl_add equ 08000C290h ; DRAM Configuration Low address dch_add equ 08000C294h ; DRAM Configuration High address ddr_add equ 08000C298h ; DRAM Delay Line Register address ;--------------------------------------------------------------------- ; DRAM Timing Low Address ;--------------------------------------------------------------------- ; CAS Latency(dtl) tcl equ dtl_add tcl_data equ 0FFFFFFF8h ; CAS Latency (3bit) tcl_2 equ 000000001h ; CAS 2 tcl_25 equ 000000005h ; CAS 2.5 tcl_3 equ 000000002h ; CAS 3 ; Row Cycle Time(dtl) trc equ dtl_add trc_data equ 0FFFFFF0Fh ; Row Cycle Time (4bit) trc_7 equ 000000000h ; 7 clock trc_8 equ 000000010h ; 8 clock trc_9 equ 000000020h ; 9 clock trc_10 equ 000000030h ; 10clock trc_11 equ 000000040h ; 11clock trc_12 equ 000000050h ; 12clock trc_13 equ 000000060h ; 13clock trc_14 equ 000000070h ; 14clock trc_15 equ 000000080h ; 15clock trc_16 equ 000000090h ; 16clock trc_17 equ 0000000A0h ; 17clock trc_18 equ 0000000B0h ; 18clock trc_19 equ 0000000C0h ; 19clock trc_20 equ 0000000D0h ; 20clock trc_21 equ 0000000E0h ; 21clock trc_22 equ 0000000F0h ; 22clock ; Row Refresh Cycle Time(dtl) trfc equ dtl_add trfc_data equ 0FFFFF0FFh ; Row Refresh Cycle Time (4bit) trfc_9 equ 000000000h ; 9 clock trfc_10 equ 000000100h ; 10clock trfc_11 equ 000000200h ; 11clock trfc_12 equ 000000300h ; 12clock trfc_13 equ 000000400h ; 13clock trfc_14 equ 000000500h ; 14clock trfc_15 equ 000000600h ; 15clock trfc_16 equ 000000700h ; 16clock trfc_17 equ 000000800h ; 17clock trfc_18 equ 000000900h ; 18clock trfc_19 equ 000000A00h ; 19clock trfc_20 equ 000000B00h ; 20clock trfc_21 equ 000000C00h ; 21clock trfc_22 equ 000000D00h ; 22clock trfc_23 equ 000000E00h ; 23clock trfc_24 equ 000000F00h ; 24clock ; RAS to CAS Delay(dtl) trcd equ dtl_add trcd_data equ 0FFFF8FFFh ; RAS to CAS Delay (3bit) trcd_2 equ 000002000h ; 2 clock trcd_3 equ 000003000h ; 3 clock trcd_4 equ 000004000h ; 4 clock trcd_5 equ 000005000h ; 5 clock trcd_6 equ 000006000h ; 6 clock ; RAS to RAS Delay(dtl) trrd equ dtl_add trrd_data equ 0FFF8FFFFh ; RAS to RAS Delay (3bit) trrd_2 equ 000020000h ; 2 clock trrd_3 equ 000030000h ; 3 clock trrd_4 equ 000040000h ; 4 clock ; Min. RAS active time(dtl) tras equ dtl_add tras_data equ 0FF0FFFFFh ; Min. RAS active time (4bit) tras_5 equ 000500000h ; 5 clock tras_6 equ 000600000h ; 6 clock tras_7 equ 000700000h ; 7 clock tras_8 equ 000800000h ; 8 clock tras_9 equ 000900000h ; 9 clock tras_10 equ 000A00000h ; 10clock tras_11 equ 000B00000h ; 11clock tras_12 equ 000C00000h ; 12clock tras_13 equ 000D00000h ; 13clock tras_14 equ 000E00000h ; 14clock tras_15 equ 000F00000h ; 15clock ; Row Precharge Time(dtl) trp equ dtl_add trp_data equ 0F8FFFFFFh ; Row Precharge Time (3bit) trp_2 equ 002000000h ; 2 clock trp_3 equ 003000000h ; 3 clock trp_4 equ 004000000h ; 4 clock trp_5 equ 005000000h ; 5 clock trp_6 equ 006000000h ; 6 clock ; Write Recovery Time(dtl) twr equ dtl_add twr_data equ 0EFFFFFFFh ; Write Recovery Time (1bit) twr_2 equ 000000000h ; 2 clock twr_3 equ 010000000h ; 3 clock ;--------------------------------------------------------------------- ; DRAM Timing High Address ;--------------------------------------------------------------------- ; Write to read delay(dth) twtr equ dth_add twtr_data equ 0FFFFFFFEh ; Write to read delay (1bit) twtr_1 equ 000000001h ; 1 clock twtr_2 equ 000000002h ; 2 clock ; Read to write delay(dth) trwt equ dth_add trwt_data equ 0FFFFFF8Fh ; Read to write delay (3bit) trwt_1 equ 000000000h ; 1 clock trwt_2 equ 000000010h ; 2 clock trwt_3 equ 000000020h ; 3 clock trwt_4 equ 000000030h ; 4 clock trwt_5 equ 000000040h ; 5 clock trwt_6 equ 000000050h ; 6 clock ; Refresh Rate(dth) tref equ dth_add tref_data equ 0FFFFE0FFh ; Refresh Rate (5bit) tref_100_156 equ 000000000h ; 100MHz 15.6us tref_133_156 equ 000000100h ; 133MHz 15.6us tref_166_156 equ 000000200h ; 166MHz 15.6us tref_200_156 equ 000000300h ; 200MHz 15.6us tref_100_78 equ 000000800h ; 100MHz 7.8us tref_133_78 equ 000000900h ; 133MHz 7.8us tref_166_78 equ 000000A00h ; 166MHz 7.8us tref_200_78 equ 000000B00h ; 200MHz 7.8us tref_100_39 equ 000001000h ; 100MHz 3.9us tref_133_39 equ 000001100h ; 133MHz 3.9us tref_166_39 equ 000001200h ; 166MHz 3.9us tref_200_39 equ 000001300h ; 200MHz 3.9us ; Write CAS latency(dth) twcl equ dth_add twcl_data equ 0FF8FFFFFh ; Write CAS latency (3bit) twcl_1 equ 000000000h ; 1 clock twcl_2 equ 000100000h ; 2 clock ;--------------------------------------------------------------------- ; DRAM Configuration Low Address ;--------------------------------------------------------------------- ; DLL Disabled(dcl) dll equ dcl_add dll_data equ 0FFFFFFFEh ; DLL disabled (1bit) dll_enable equ 000000000h ; Enabled(default) dll_disable equ 000000001h ; Disabled ; Dimm Drive Strength(dcl) dds equ dcl_add dds_data equ 0FFFFFFFDh ; Dimm Drive Strength (1bit) dds_normal equ 000000000h ; Normal(Default) dds_weak equ 000000002h ; Weak (Beware) ; Read/Write Qued Bypass(dcl) rwqbp equ dcl_add rwqbp_data equ 0FFFF3FFFh ; Read/Write Qued Bypass (2bit) rwqbp_2x equ 000000000h ; 2x rwqbp_4x equ 000004000h ; 4x rwqbp_8x equ 000008000h ; 8x rwqbp_16x equ 00000C000h ; 16x ; Bypass Max(dcl) bpm equ dcl_add bpm_data equ 0F1FFFFFFh ; Bypass Max (3bit) bpm_0x equ 000000000h ; 0x (Disabled) bpm_1x equ 002000000h ; 1x bpm_2x equ 004000000h ; 2x bpm_3x equ 006000000h ; 3x bpm_4x equ 008000000h ; 4x bpm_5x equ 00A000000h ; 5x bpm_6x equ 00C000000h ; 6x bpm_7x equ 00E000000h ; 7x ; Command Rate(dcl) cr equ dcl_add cr_data equ 0EFFFFFFFh ; Command Rate (1bit) cr_1t equ 000000000h ; 1T cr_2t equ 010000000h ; 2T ;--------------------------------------------------------------------- ; DRAM Configuration High Address ;--------------------------------------------------------------------- ; Maximum Async Latency(dch) async equ dch_add async_data equ 0FFFFFFF0h ; Maximum Async Latency (4bit) async_0 equ 000000000h ; 0 ns async_1 equ 000000001h ; 1 ns async_2 equ 000000002h ; 2 ns async_3 equ 000000003h ; 3 ns async_4 equ 000000004h ; 4 ns async_5 equ 000000005h ; 5 ns async_6 equ 000000006h ; 6 ns async_7 equ 000000007h ; 7 ns async_8 equ 000000008h ; 8 ns async_9 equ 000000009h ; 9 ns async_10 equ 00000000Ah ; 10ns async_11 equ 00000000Bh ; 11ns async_12 equ 00000000Ch ; 12ns async_13 equ 00000000Dh ; 13ns async_14 equ 00000000Eh ; 14ns async_15 equ 00000000Fh ; 15ns ; Read Preamble(dch) rp equ dch_add rp_data equ 0FFFFF0FFh ; Read Preamble (4bit) rp_20 equ 000000000h ; 2.0ns rp_25 equ 000000100h ; 2.5ns rp_30 equ 000000200h ; 3.0ns rp_35 equ 000000300h ; 3.5ns rp_40 equ 000000400h ; 4.0ns rp_45 equ 000000500h ; 4.5ns rp_50 equ 000000600h ; 5.0ns rp_55 equ 000000700h ; 5.5ns rp_60 equ 000000800h ; 6.0ns rp_65 equ 000000900h ; 6.5ns rp_70 equ 000000A00h ; 7.0ns rp_75 equ 000000B00h ; 7.5ns rp_80 equ 000000C00h ; 8.0ns rp_85 equ 000000D00h ; 8.5ns rp_90 equ 000000E00h ; 9.0ns rp_95 equ 000000F00h ; 9.5ns ; Idle Cycle Limit(dch) icl equ dch_add icl_data equ 0FFF8FFFFh ; Idle Cycle Limit (3bit) icl_0 equ 000000000h ; 0 clock icl_4 equ 000010000h ; 4 clock icl_8 equ 000020000h ; 8 clock icl_16 equ 000030000h ; 16clock icl_32 equ 000040000h ; 32clock icl_64 equ 000050000h ; 64clock icl_128 equ 000060000h ; 128clock icl_256 equ 000070000h ; 256clock ; Dynamic idle cycle counter enable(dch) dicc equ dch_add dicc_data equ 0FFF7FFFFh ; Dynamic idle cycle limit (1bit) dicc_disable equ 000000000h ; disabled dicc_enable equ 000080000h ; enabled ; Memory Clock Frequency(dch) mcf equ dch_add mcf_data equ 0FF8FFFFFh ; Memory Clock Frequency (3bit) mcf_100 equ 000000000h ; 100MHz mcf_120 equ 000100000h ; 120MHz mcf_133 equ 000200000h ; 133MHz mcf_140 equ 000300000h ; 140MHz mcf_150 equ 000400000h ; 150MHz mcf_166 equ 000500000h ; 166MHz mcf_180 equ 000600000h ; 180MHz mcf_200 equ 000700000h ; 200MHz (1:1) ;--------------------------------------------------------------------- ; DRAM DQS Delay Line Register ;--------------------------------------------------------------------- ; DQS Slew Value(ddr) dqs equ ddr_add dqs_data equ 0FF00FFFFh ; Delay Line Adjust (8bit) dqs_1 equ 000010000h ; 1 dqs_2 equ 000020000h ; 2 dqs_3 equ 000030000h ; 3 dqs_4 equ 000040000h ; 4 dqs_5 equ 000050000h ; 5 dqs_6 equ 000060000h ; 6 dqs_7 equ 000070000h ; 7 dqs_8 equ 000080000h ; 8 dqs_9 equ 000090000h ; 9 dqs_10 equ 0000A0000h ; 10 dqs_255 equ 000FF0000h ; 255 ; DQS Slew Control(ddr) dqsc equ ddr_add dqsc_data equ 0FCFFFFFFh ; Adjust DQS (1bit) & (1bit) dqsc_slow equ 001000000h ; Slower DQS dqsc_fast equ 002000000h ; Faster DQS ;--------------------------------------------------------------------------------------------------- ;---------------------------PCI ROM Header---------------------------------------------------------- ;--------------------------------------------------------------------------------------------------- ROM_SIZE_IN_BLOCK = 1 ; 1 means ROM size is 1 block (512 bytes) ROM_SIZE_IN_BYTE = ROM_SIZE_IN_BLOCK * 512 VENDOR_ID equ 10DEh ; PCI Vendor ID (must match yout ethernet vendor id) ; exp: 10DE = nVidia DEVICE_ID equ 01E0h ; PCI Device ID (must match yout ethernet devicie id) ; exp: 01E0h = nforce2 NIC ROMStart: db 0x055, 0x0AA ; ROM Header 55,AA -> Bootable rom db (ROMEnd - ROMStart)/512 ; ROM Size in 512byte jmp MAIN db 0 ; checksum, to be filled in later TIMES 18h-($-$$) DB 0 ; padding zeros to offset 18h DW PCIHDR ; pointer to PCI Header DW PNPHDR ; pointer to PnP Expansion Header PCIHDR: DB 'PCIR' ; PCI data structure signature DW VENDOR_ID ; vendor ID (must match real PCI device) DW DEVICE_ID ; device ID (must match real PCI device) DW 0 ; pointer to vital product data (0=none) DW 24 ; PCI data structure length [B] DB 0 ; PCI data structure revision (0=PCI 2.1) DB 2,0,0 ; PCI device class code (2=network ctrlr, 0=eth.) DW ROM_SIZE_IN_BLOCK ; ROM size in 512B blocks DW 0 ; revision level of code DB 0 ; code type (0=x86 compitable) DB 80h ; last image indicator DW 0 ; reserved PNPHDR: DB '$PnP' ; PnP data structure signature DB 1 ; PnP structure revision DB 2 ; PnP structure length (in 16B blocks) DW 0 ; offset to next header (0-none) DB 0 ; reserved DB 33h ; PnP structure checksum DD 0 ; device identifier DW 0 ; pointer to manufacturer string DW 0 ; pointer to productname string DB 2,0,0 ; device class code (2=network ctrlr, 0=eth.) DB 64h ; device indicators (64h - shadowable,cacheable,not only for boot,IPL device) DW 0 ; boot connection vector (0-none) DW 0 ; disconnect vector (0-none) DW 0 ; bootstrap entry vector (0-none) DW 0 ; reserved DW 0 ; static resource info vector (0-none) ;--------------------------------------------------------------------------------------------------- ;---------------------------SUB-ROUTINE------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------- macro MTT 0,1,2 { mov eax,0 ; copy register address mov ebx,1 ; copy register data mov dx,address ; set port address out dx,eax ; send address through the port mov dx,data ; set port data in eax,dx ; receive default data and eax,2 ; set data in eax or eax,ebx ; change default data out dx,eax ; send data through data port } macro SAVE ; Save all register that will be affected by our code { pushfd push eax push ebx push bx push dx push si push ds push bp } macro RETURN ; Restore register contents { pop bp pop ds pop si pop dx pop bx pop ebx pop eax popfd retf ; return far to system bios routine } ;--------------------------------------------------------------------------------------------------- ;---------------------------------------MAIN-ROUTINE------------------------------------------------ ;--------------------------------------------------------------------------------------------------- times (256)-($-$$) db 0 ; locate Main routine at 100h MAIN: SAVE ;---------------------------------------------------------------------------------------------------- ; Patch A64 Memory Timing MTT async,async_7,async_data ; Set max async latency to 7ns ;---------------------------------------------------------------------------------------------------- RETURN times (ROM_SIZE_IN_BYTE-$) db 0 ; The last byte (512th) will be the patch_byte for the checksum ; patch_byte is calculated and automagically inserted below PREV_CHKSUM = 0 repeat $ load CHKSUM byte from %-1 CHKSUM = (PREV_CHKSUM + CHKSUM) mod 0x100 PREV_CHKSUM = CHKSUM end repeat store byte (0x100 - CHKSUM) at ($-1) ; store the patch_byte ROMEnd: ;---------------------------------------CODE END----------------------------------------------------- ; How to set you memory timing? ; Just type MTT<space>timing name,timing value,timing data ; Exp : async memory to 7.0ns would be -> MTT async,async_7,async_data ; Press F9 to compile it with flat assembler ; ;----------------------------------------------------------------------------------------------------

Hi, Its a source code for Boot able ISA ROM Been using and developing it for quite sometimes... I install it as ISA ROM where it will get invoke by bios when system bootup Oh this is... AMD 64 DDR version. Use fasmw version 1.67 to compile this source http://flatassembler.net/download.php it will compile pure ISA ROM with the source i provide here Install it on my bios with cbrom version 2.07 exp: cbrom biosname.bin /isa patch.bin Any thought,comment, developement, bugs... are welcome credit : Master pinczakko, polygon and etc Thank you, tictac Ok here simple example how to set it - max async latency to 7ns ;--------------------------------------------------------------------------------------------------- ; AMD Athlon 64 DDR ROM Patcher Rev 3.0a simple version ;--------------------------------------------------------------------------------------------------- ; ; Source code writen by tictac ; Website : z6.invisionfree.com/tictac ; Note : Free to be distribute/mod , Use it at your own risk ; ;--------------------------------------------------------------------------------------------------- ;------------------------------CODE DEFINITION------------------------------------------------------ ;--------------------------------------------------------------------------------------------------- use16 ; 16bit mode address equ 0CF8h ; address port data equ 0CFCh ; data port dtl_add equ 08000C288h ; DRAM Timing Low address dth_add equ 08000C28Ch ; DRAM Timing High address dcl_add equ 08000C290h ; DRAM Configuration Low address dch_add equ 08000C294h ; DRAM Configuration High address ddr_add equ 08000C298h ; DRAM Delay Line Register address ;--------------------------------------------------------------------- ; DRAM Timing Low Address ;--------------------------------------------------------------------- ; CAS Latency(dtl) tcl equ dtl_add tcl_data equ 0FFFFFFF8h ; CAS Latency (3bit) tcl_2 equ 000000001h ; CAS 2 tcl_25 equ 000000005h ; CAS 2.5 tcl_3 equ 000000002h ; CAS 3 ; Row Cycle Time(dtl) trc equ dtl_add trc_data equ 0FFFFFF0Fh ; Row Cycle Time (4bit) trc_7 equ 000000000h ; 7 clock trc_8 equ 000000010h ; 8 clock trc_9 equ 000000020h ; 9 clock trc_10 equ 000000030h ; 10clock trc_11 equ 000000040h ; 11clock trc_12 equ 000000050h ; 12clock trc_13 equ 000000060h ; 13clock trc_14 equ 000000070h ; 14clock trc_15 equ 000000080h ; 15clock trc_16 equ 000000090h ; 16clock trc_17 equ 0000000A0h ; 17clock trc_18 equ 0000000B0h ; 18clock trc_19 equ 0000000C0h ; 19clock trc_20 equ 0000000D0h ; 20clock trc_21 equ 0000000E0h ; 21clock trc_22 equ 0000000F0h ; 22clock ; Row Refresh Cycle Time(dtl) trfc equ dtl_add trfc_data equ 0FFFFF0FFh ; Row Refresh Cycle Time (4bit) trfc_9 equ 000000000h ; 9 clock trfc_10 equ 000000100h ; 10clock trfc_11 equ 000000200h ; 11clock trfc_12 equ 000000300h ; 12clock trfc_13 equ 000000400h ; 13clock trfc_14 equ 000000500h ; 14clock trfc_15 equ 000000600h ; 15clock trfc_16 equ 000000700h ; 16clock trfc_17 equ 000000800h ; 17clock trfc_18 equ 000000900h ; 18clock trfc_19 equ 000000A00h ; 19clock trfc_20 equ 000000B00h ; 20clock trfc_21 equ 000000C00h ; 21clock trfc_22 equ 000000D00h ; 22clock trfc_23 equ 000000E00h ; 23clock trfc_24 equ 000000F00h ; 24clock ; RAS to CAS Delay(dtl) trcd equ dtl_add trcd_data equ 0FFFF8FFFh ; RAS to CAS Delay (3bit) trcd_2 equ 000002000h ; 2 clock trcd_3 equ 000003000h ; 3 clock trcd_4 equ 000004000h ; 4 clock trcd_5 equ 000005000h ; 5 clock trcd_6 equ 000006000h ; 6 clock ; RAS to RAS Delay(dtl) trrd equ dtl_add trrd_data equ 0FFF8FFFFh ; RAS to RAS Delay (3bit) trrd_2 equ 000020000h ; 2 clock trrd_3 equ 000030000h ; 3 clock trrd_4 equ 000040000h ; 4 clock ; Min. RAS active time(dtl) tras equ dtl_add tras_data equ 0FF0FFFFFh ; Min. RAS active time (4bit) tras_5 equ 000500000h ; 5 clock tras_6 equ 000600000h ; 6 clock tras_7 equ 000700000h ; 7 clock tras_8 equ 000800000h ; 8 clock tras_9 equ 000900000h ; 9 clock tras_10 equ 000A00000h ; 10clock tras_11 equ 000B00000h ; 11clock tras_12 equ 000C00000h ; 12clock tras_13 equ 000D00000h ; 13clock tras_14 equ 000E00000h ; 14clock tras_15 equ 000F00000h ; 15clock ; Row Precharge Time(dtl) trp equ dtl_add trp_data equ 0F8FFFFFFh ; Row Precharge Time (3bit) trp_2 equ 002000000h ; 2 clock trp_3 equ 003000000h ; 3 clock trp_4 equ 004000000h ; 4 clock trp_5 equ 005000000h ; 5 clock trp_6 equ 006000000h ; 6 clock ; Write Recovery Time(dtl) twr equ dtl_add twr_data equ 0EFFFFFFFh ; Write Recovery Time (1bit) twr_2 equ 000000000h ; 2 clock twr_3 equ 010000000h ; 3 clock ;--------------------------------------------------------------------- ; DRAM Timing High Address ;--------------------------------------------------------------------- ; Write to read delay(dth) twtr equ dth_add twtr_data equ 0FFFFFFFEh ; Write to read delay (1bit) twtr_1 equ 000000001h ; 1 clock twtr_2 equ 000000002h ; 2 clock ; Read to write delay(dth) trwt equ dth_add trwt_data equ 0FFFFFF8Fh ; Read to write delay (3bit) trwt_1 equ 000000000h ; 1 clock trwt_2 equ 000000010h ; 2 clock trwt_3 equ 000000020h ; 3 clock trwt_4 equ 000000030h ; 4 clock trwt_5 equ 000000040h ; 5 clock trwt_6 equ 000000050h ; 6 clock ; Refresh Rate(dth) tref equ dth_add tref_data equ 0FFFFE0FFh ; Refresh Rate (5bit) tref_100_156 equ 000000000h ; 100MHz 15.6us tref_133_156 equ 000000100h ; 133MHz 15.6us tref_166_156 equ 000000200h ; 166MHz 15.6us tref_200_156 equ 000000300h ; 200MHz 15.6us tref_100_78 equ 000000800h ; 100MHz 7.8us tref_133_78 equ 000000900h ; 133MHz 7.8us tref_166_78 equ 000000A00h ; 166MHz 7.8us tref_200_78 equ 000000B00h ; 200MHz 7.8us tref_100_39 equ 000001000h ; 100MHz 3.9us tref_133_39 equ 000001100h ; 133MHz 3.9us tref_166_39 equ 000001200h ; 166MHz 3.9us tref_200_39 equ 000001300h ; 200MHz 3.9us ; Write CAS latency(dth) twcl equ dth_add twcl_data equ 0FF8FFFFFh ; Write CAS latency (3bit) twcl_1 equ 000000000h ; 1 clock twcl_2 equ 000100000h ; 2 clock ;--------------------------------------------------------------------- ; DRAM Configuration Low Address ;--------------------------------------------------------------------- ; DLL Disabled(dcl) dll equ dcl_add dll_data equ 0FFFFFFFEh ; DLL disabled (1bit) dll_enable equ 000000000h ; Enabled(default) dll_disable equ 000000001h ; Disabled ; Dimm Drive Strength(dcl) dds equ dcl_add dds_data equ 0FFFFFFFDh ; Dimm Drive Strength (1bit) dds_normal equ 000000000h ; Normal(Default) dds_weak equ 000000002h ; Weak (Beware) ; Read/Write Qued Bypass(dcl) rwqbp equ dcl_add rwqbp_data equ 0FFFF3FFFh ; Read/Write Qued Bypass (2bit) rwqbp_2x equ 000000000h ; 2x rwqbp_4x equ 000004000h ; 4x rwqbp_8x equ 000008000h ; 8x rwqbp_16x equ 00000C000h ; 16x ; Bypass Max(dcl) bpm equ dcl_add bpm_data equ 0F1FFFFFFh ; Bypass Max (3bit) bpm_0x equ 000000000h ; 0x (Disabled) bpm_1x equ 002000000h ; 1x bpm_2x equ 004000000h ; 2x bpm_3x equ 006000000h ; 3x bpm_4x equ 008000000h ; 4x bpm_5x equ 00A000000h ; 5x bpm_6x equ 00C000000h ; 6x bpm_7x equ 00E000000h ; 7x ; Command Rate(dcl) cr equ dcl_add cr_data equ 0EFFFFFFFh ; Command Rate (1bit) cr_1t equ 000000000h ; 1T cr_2t equ 010000000h ; 2T ;--------------------------------------------------------------------- ; DRAM Configuration High Address ;--------------------------------------------------------------------- ; Maximum Async Latency(dch) async equ dch_add async_data equ 0FFFFFFF0h ; Maximum Async Latency (4bit) async_0 equ 000000000h ; 0 ns async_1 equ 000000001h ; 1 ns async_2 equ 000000002h ; 2 ns async_3 equ 000000003h ; 3 ns async_4 equ 000000004h ; 4 ns async_5 equ 000000005h ; 5 ns async_6 equ 000000006h ; 6 ns async_7 equ 000000007h ; 7 ns async_8 equ 000000008h ; 8 ns async_9 equ 000000009h ; 9 ns async_10 equ 00000000Ah ; 10ns async_11 equ 00000000Bh ; 11ns async_12 equ 00000000Ch ; 12ns async_13 equ 00000000Dh ; 13ns async_14 equ 00000000Eh ; 14ns async_15 equ 00000000Fh ; 15ns ; Read Preamble(dch) rp equ dch_add rp_data equ 0FFFFF0FFh ; Read Preamble (4bit) rp_20 equ 000000000h ; 2.0ns rp_25 equ 000000100h ; 2.5ns rp_30 equ 000000200h ; 3.0ns rp_35 equ 000000300h ; 3.5ns rp_40 equ 000000400h ; 4.0ns rp_45 equ 000000500h ; 4.5ns rp_50 equ 000000600h ; 5.0ns rp_55 equ 000000700h ; 5.5ns rp_60 equ 000000800h ; 6.0ns rp_65 equ 000000900h ; 6.5ns rp_70 equ 000000A00h ; 7.0ns rp_75 equ 000000B00h ; 7.5ns rp_80 equ 000000C00h ; 8.0ns rp_85 equ 000000D00h ; 8.5ns rp_90 equ 000000E00h ; 9.0ns rp_95 equ 000000F00h ; 9.5ns ; Idle Cycle Limit(dch) icl equ dch_add icl_data equ 0FFF8FFFFh ; Idle Cycle Limit (3bit) icl_0 equ 000000000h ; 0 clock icl_4 equ 000010000h ; 4 clock icl_8 equ 000020000h ; 8 clock icl_16 equ 000030000h ; 16clock icl_32 equ 000040000h ; 32clock icl_64 equ 000050000h ; 64clock icl_128 equ 000060000h ; 128clock icl_256 equ 000070000h ; 256clock ; Dynamic idle cycle counter enable(dch) dicc equ dch_add dicc_data equ 0FFF7FFFFh ; Dynamic idle cycle limit (1bit) dicc_disable equ 000000000h ; disabled dicc_enable equ 000080000h ; enabled ; Memory Clock Frequency(dch) mcf equ dch_add mcf_data equ 0FF8FFFFFh ; Memory Clock Frequency (3bit) mcf_100 equ 000000000h ; 100MHz mcf_120 equ 000100000h ; 120MHz mcf_133 equ 000200000h ; 133MHz mcf_140 equ 000300000h ; 140MHz mcf_150 equ 000400000h ; 150MHz mcf_166 equ 000500000h ; 166MHz mcf_180 equ 000600000h ; 180MHz mcf_200 equ 000700000h ; 200MHz (1:1) ;--------------------------------------------------------------------- ; DRAM DQS Delay Line Register ;--------------------------------------------------------------------- ; DQS Slew Value(ddr) dqs equ ddr_add dqs_data equ 0FF00FFFFh ; Delay Line Adjust (8bit) dqs_1 equ 000010000h ; 1 dqs_2 equ 000020000h ; 2 dqs_3 equ 000030000h ; 3 dqs_4 equ 000040000h ; 4 dqs_5 equ 000050000h ; 5 dqs_6 equ 000060000h ; 6 dqs_7 equ 000070000h ; 7 dqs_8 equ 000080000h ; 8 dqs_9 equ 000090000h ; 9 dqs_10 equ 0000A0000h ; 10 dqs_255 equ 000FF0000h ; 255 ; DQS Slew Control(ddr) dqsc equ ddr_add dqsc_data equ 0FCFFFFFFh ; Adjust DQS (1bit) & (1bit) dqsc_slow equ 001000000h ; Slower DQS dqsc_fast equ 002000000h ; Faster DQS ;--------------------------------------------------------------------------------------------------- ;---------------------------ROM Header-------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------- ROM_SIZE_IN_BLOCK = 1 ; 1 means ROM size is 1 block (512 bytes) ROM_SIZE_IN_BYTE = ROM_SIZE_IN_BLOCK * 512 ROMStart: db 0x055, 0x0AA ; ROM Header 55,AA -> Bootable rom db (ROMEnd - ROMStart)/512 ; ROM Size in 512byte jmp MAIN db 0 ; checksum, to be filled in later ;--------------------------------------------------------------------------------------------------- ;---------------------------SUB-ROUTINE------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------- macro MTT 0,1,2 { mov eax,0 ; copy register address mov ebx,1 ; copy register data mov dx,address ; set port address out dx,eax ; send address through the port mov dx,data ; set port data in eax,dx ; receive default data and eax,2 ; set data in eax or eax,ebx ; change default data out dx,eax ; send data through data port } macro SAVE ; Save all register that will be affected by our code { pushfd push eax push ebx push bx push dx push si push ds push bp } macro RETURN ; Restore register contents { pop bp pop ds pop si pop dx pop bx pop ebx pop eax popfd retf ; return far to system bios routine } ;--------------------------------------------------------------------------------------------------- ;---------------------------------------MAIN-ROUTINE------------------------------------------------ ;--------------------------------------------------------------------------------------------------- times (256)-($-$$) db 0 ; locate Main routine at 100h MAIN: SAVE ;---------------------------------------------------------------------------------------------------- ; Patch A64 Memory Timing MTT async,async_7,async_data ; Set max async latency to 7ns ;---------------------------------------------------------------------------------------------------- RETURN times (ROM_SIZE_IN_BYTE-$) db 0 ; The last byte (512th) will be the patch_byte for the checksum ; patch_byte is calculated and automagically inserted below PREV_CHKSUM = 0 repeat $ load CHKSUM byte from %-1 CHKSUM = (PREV_CHKSUM + CHKSUM) mod 0x100 PREV_CHKSUM = CHKSUM end repeat store byte (0x100 - CHKSUM) at ($-1) ; store the patch_byte ROMEnd: ;---------------------------------------CODE END----------------------------------------------------- ; How to set you memory timing? ; Just type MTT<space>timing name,timing value,timing data ; Exp : async memory to 7.0ns would be -> MTT async,async_7,async_data ; Press F9 to compile it with flat assembler ; ;----------------------------------------------------------------------------------------------------

Keep it simple and direct english... :nod:

KHX3200ULK2 = Samsung TCCD :nod:

if you disable dual channel mode... will the board boot?

emm..my suggestion.... instead of doing the memory test at SPD default voltage ... is it possible to apply DDR Voltage from setting we save in bios....

i'm here :nod:

yeah.. at least add some Change Log.. so that user know what they are flashing to.. What Version of : - NVMM - NVRAID - NVLAN installed?

i got it on my website including Vcore pencil mod You can read it here: :nod: http://www.tictac.katrourke.com/modules.ph...=showpage&pid=4

DFI Lan Party B 6-19 XT Change Log from original 6-19 3D Fire R2 ---------------------------------------------------- 1 Enhance Memory Bandwith 2 Soft L12 3 New Boot Up Logo Size = 352KB Download Link: http://www.tictac.katrourke.com/bios/DFI-LPB-619XT.zip Preview Quality Check -------------- # Comparison done @ 200MHz x 8.0 = 1.6Ghz # Timing : 2.5-3-3-3-11-1T # Memory : 2 sticks TwinMOS + 1 Stick KVR = 768MB a) 619 3D Fire R2 ----------------- mem latency : 91.9 ns mem read : 2926 mb/sec mem write : 1112 mb/sec 2) 619 XT --------- mem latency : 91.8 ns mem read : 2962 mb/sec mem write : 1128 mb/sec

D26 Mantarays XT 1T

i havent really push my TwinMOS SP yet... as my Proc only max arround 1.6-1.7GHz with stock cooling thanks.. i will try your timing later BTW the Vcore mod... i tested with prime... 5hours stable so far... & still running :nod: