jkkeeton Posted May 14, 2005 Posted May 14, 2005 k first off i was using geil ultra x 3200 that would not get stable for anything went through hell and back with it. i got this ocz 4000 and it runs at 2-2-2-6 3.3v stable as can be right away i got prime stable and memtest stable. 2.4 ghz and i think i can do more but im not going to yet i need to get a better heatsink and fan i have stock. for newer winchester users run this if your using ocz 4000 gold vx and you will be happy. the only thing i changed was i put cpu vid specail at 123% to make 1.55v FSB Bus Frequency - 240 LDT/FSB Frequency Ration - Auto CPU/FSB Frequency Ratio - Auto PCI eXpress Frequency - 100Mhz CPU VID StartUp Value - 1.500v CPU VID Control - 1.300v CPU VID Special Control - Above VID * 126% LDT Voltage Control - 1.20v Chip Set Voltage Control - 1.50v DRAM Voltage Control - 3.30v DRAM Configuration Settings: DRAM Frequency Set - 200 (DRAM/FSB:1/01) Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2.0 RAS# to CAS# delay (Trcd) - 02 Bus Clocks Min RAS# active time (Tras) - 06 Bus Clocks Row precharge time (Trp) - 02 Bus Clocks Row Cycle time (Trc) - 07 Bus Clocks Row refresh cyc time (Trfc) - 16 Bus Clocks Row to Row delay (Trrd) - 03 Bus Clocks Write recovery time (Twr) - 02 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trwt) - 03 Bus Clocks Refresh Period (Tref) - Auto Write CAS Latency (Twcl) - Auto DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - Level 8 DRAM Data Drive Strength - Level 2 Max Async Latency - Auto Read Preamble Time - Auto IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(8 Bursts) Share this post Link to post Share on other sites More sharing options...
DougTanner Posted May 15, 2005 Posted May 15, 2005 I've got my VX upto 260 MHz 2-2-2-6 so far with 3.4V (it really doesn't like 3.5V). It's too bad my processor tops out at 255 *10, I want to run my RAM at full potential T_T Share this post Link to post Share on other sites More sharing options...
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