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Couple Of Quick Runs With The Dfi Lp Dk X48-t2rsb Plus


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After sitting on the shelf for several weeks, I finally got a couple of other boards cleared off the bench to be able to set this board up. These are some settings I put together over the weekend. So far the board seems really easy to work with.

 

 

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LP DK X48-T2RSB Plus - E8600, 500x8, Page 1 Of 3

 

DFI DK X48-T2RSB PLUS, 08/29 BIOS

500x8, Memory 1200MHz

E8600

2x1GB Cell Shock PC2-8000 1000MHz 4-4-4-12

SAPPHIRE 4870

Orange Slots Used For Memory

 

click for larger image

main_s.jpg volt_s.jpg

 

click for larger image

dram_1_s.jpg dram_2_s.jpg

 

click for larger image

clock_1_s.jpg clock_2_s.jpg

 

click for larger image

phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................0
CPU Clock Ratio...........................8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................500 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................100ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................333/800
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled
SATA Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Control...........................Auto
CPU VID Special Add.......................101%
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.543V
CPU VTT Voltage...........................1.180V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................00
CPU GTL 0/2 REF Volt......................0.636X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.67X

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................4
REF to ACT Delay (tRFC)...................36
Performance Level.........................8
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................1
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................5
ALL PRE to Refresh........................4

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DRAM CLK Driving Strength.................Level 6
DRAM Data Driving Strength................Level 8
Ch1 DLL Default Skew Model................Model 5
Ch2 DLL Default Skew Model................Model 5

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 1539ps
DIMM 2 Clock fine delay...................Current 345ps
DIMM 1 Control fine delay.................Current 489ps
DIMM 2 Control fine delay.................Current 434ps
Ch 1 Command fine delay...................Current 489ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 256ps
DIMM 4 Clock fine delay...................Current 300ps
DIMM 3 Control fine delay.................Current 523ps
DIMM 4 Control fine delay.................Current 445ps
Ch 2 Command fine delay...................Current 523ps

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

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1200_memtest_xp_s.jpg

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LP DK X48-T2RSB Plus - E8600, 500x8, Page 2 Of 3

 

 

XP SP3

 

 

click for larger image

1200_occt_xp_s.jpg

 

 

click for larger image

1200_3d06_xp_s.jpg

 

 

1200_crysis_xp.jpg1200_ut3_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 14min 03sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1200_everest_xp_s.jpg

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LP DK X48-T2RSB Plus - E8600, 500x8, Page 3 Of 3

 

 

Vista 64 Bit SP1

 

 

click for larger image

1200_occt_64_s.jpg

 

 

click for larger image

1200_3d06_64_s.jpg

 

 

click for larger image

1200_3dvan_64_s.jpg

 

 

click for larger image

1200_pcvan_64_s.jpg

 

 

1200_crysis_64.jpg1200_ut3_64.jpg

 

 

3dx Max w/V-ray

Time to render: 15min 20sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1200_everest_64_s.jpg

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LP DK X48-T2RSB Plus - E8600, 550x8, Page 1 Of 3

 

 

DFI DK X48-T2RSB PLUS, 08/29 BIOS

550x8, Memory 1110MHz

E8600

2x1GB Cell Shock PC2-8000 1000MHz 4-4-4-12

SAPPHIRE 4870

Orange Slots Used For Memory

 

click for larger image

main_s.jpg volt_s.jpg

 

click for larger image

dram_1_s.jpg dram_2_s.jpg

 

click for larger image

clock_1_s.jpg clock_2_s.jpg

 

click for larger image

phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
Shutdown After AC Loss....................Disabled
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio...........................8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................550 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................200ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz
PCIE Slot Config..........................1X 1X

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Control...........................Auto
CPU VID Special Add.......................111%
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.543V
CPU VTT Voltage...........................1.210V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................00
CPU GTL 0/2 REF Volt......................0.667X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.61X

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................Auto
REF to ACT Delay (tRFC)...................Auto
Performance Level.........................Auto
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................Auto
Rank Write to Read (tWTR).................Auto
ACT to ACT Delay (tRRD)...................Auto
Read to Write Delay (tRDWR)...............Auto
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................Auto
ALL PRE to Refresh........................Auto

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DRAM CLK Driving Strength.................Level 6
DRAM Data Driving Strength................Level 8
Ch1 DLL Default Skew Model................Model 5
Ch2 DLL Default Skew Model................Model 5

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 1886ps
DIMM 2 Clock fine delay...................Current 1012ps
DIMM 1 Control fine delay.................Current 962ps
DIMM 2 Control fine delay.................Current 962ps
Ch 1 Command fine delay...................Current 1412ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 1737ps
DIMM 4 Clock fine delay...................Current 800ps
DIMM 3 Control fine delay.................Current 724ps
DIMM 4 Control fine delay.................Current 86ps
Ch 2 Command fine delay...................Current 1486ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

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550fsbcs_memtest_s.jpg

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LP DK X48-T2RSB Plus - E8600, 550x8, Page 2 Of 3

 

 

XP SP3

 

 

click for larger image

550fsbcs_occt_xp_s.jpg

 

 

click for larger image

550fsbcs_3d06_xp_s.jpg

 

 

550fsbcs_crysis_xp.jpg550fsbcs_ut3_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 12min 51sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

550fsbcs_everest_xp_s.jpg

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LP DK X48-T2RSB Plus - E8600, 550x8, Page 3 Of 3

 

 

Vista 64 Bit SP1

 

 

click for larger image

550fsbcs_occt_64_s.jpg

 

 

click for larger image

550fsbcs_3d06_64_s.jpg

 

 

click for larger image

550fsbcs_3dvan_64_s.jpg

 

 

click for larger image

550fsbcs_pcvan_64_s.jpg

 

 

550fsbcs_crysis_64.jpg550fsbcs_ut3_64.jpg

 

 

3dx Max w/V-ray

Time to render: 14min 02sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

550fsbcs_everest_64_s.jpg

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  • 1 month later...

DFI DK X48-T2RSB PLUS, E8600, 475x9.5, 2x2GB, Page 1 Of 3

 

DFI DK X48-T2RSB PLUS, 09/23 BIOS

475x9.5, Memory 1140MHz

E8600

2x2GB OCZ Flex II PC2-9200 1150MHz 5-5-5-18

SAPPHIRE 4870

Yellow Slots Used For Memory

 

click for larger image

main_s.jpg volt_s.jpg

 

click for larger image

dram1_s.jpg dram2_s.jpg

 

click for larger image

clock1_s.jpg clock2_s.jpg

 

click for larger image

phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM (EIST) Mode...........................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
O.C. Fail Retry Counter...................0
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio...........................9.5x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................475 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude.......................800mV
CPU Clock0 Skew...........................0ps
CPU Clock0 Skew...........................0ps
DRAM Speed................................333/800
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Control...........................1.41875
CPU VID Special Add.......................Auto
DRAM Voltage Control......................2.000V
SB Core/CPU PLL Voltage...................1.510V
NB Core Voltage...........................1.555V
CPU VTT Voltage...........................1.160V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
GTL+ Buffers Strength.....................Strong
Host Slew Rate............................Weak
MCH RON Offset Value......................00
MCH RTT Offset Value......................00
MCH Slew Rate Offset Value................00
MCH VREF 1 Value..........................00
MCH VREF 2 Value..........................00
MCH VREF 3 Value..........................80
CPU GTL 0/2 REF Volt......................0.648X
CPU GTL 1/3 REF Volt......................0.667X
North Bridge GTL REF Volt ................0.67X

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Enabled
Clock Setting Fine Delay..................Listed Below

CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................18
All Precharge to Act......................6
REF to ACT Delay (tRFC)...................54
Performance Level.........................7
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Read to Read (tRDRD)................Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................Auto

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DRAM CLK Driving Strength.................Level 2
DRAM Data Driving Strength................Level 6
Ch1 DLL Default Skew Model................Model 0
Ch2 DLL Default Skew Model................Model 0

Fine Delay Step Degree....................5ps


Ch1 Clock Crossing Setting................More Aggressive
DIMM 1 Clock fine delay...................Current 1840ps
DIMM 2 Clock fine delay...................Current  957ps
DIMM 1 Control fine delay.................Current 1023ps
DIMM 2 Control fine delay.................Current  434ps
Ch 1 Command fine delay...................Current  33ps

Ch2 Clock Crossing Setting................More Aggressive
DIMM 3 Clock fine delay...................Current 1840ps
DIMM 4 Clock fine delay...................Current  890ps
DIMM 3 Control fine delay.................Current  868ps
DIMM 4 Control fine delay.................Current  857ps
Ch 2 Command fine delay...................Current  33ps

Ch1Ch2 CommonClock Setting................More Aggressive

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

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1140f_lin_64_s.jpg

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DFI DK X48-T2RSB PLUS, E8600, 475x9.5, 2x2GB, Page 2 Of 3

 

XP SP3

 

 

click for larger image

1140f_occt_xp_s.jpg

 

 

click for larger image

1140f_3d06_xp_s.jpg

 

 

1140f_crysis_xp.jpg1140f_ut3_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 12min 34sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1140f_everest_xp_s.jpg

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DFI DK X48-T2RSB PLUS, E8600, 475x9.5, 2x2GB, Page 3 Of 3

 

Vista 64 Bit SP1

 

 

click for larger image

1140f_occt_64_s.jpg

 

 

click for larger image

1140f_3d06_64_s.jpg

 

 

click for larger image

1140f_3dvan_64_s.jpg

 

 

click for larger image

1140f_pcvan_64_s.jpg

 

 

1140f_crysis_64.jpg1140f_ut3_64.jpg

 

 

3dx Max w/V-ray

Time to render: 13min 41sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1140f_everest_64_s.jpg

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I'm liking that board very much, maybe I need to look into it once it releases in Germany. I have a question though, what is that program you used for testing called LinX? What does it test and does it output a score or just tell you it's stable (like OCCT)?

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I'm liking that board very much, maybe I need to look into it once it releases in Germany. I have a question though, what is that program you used for testing called LinX? What does it test and does it output a score or just tell you it's stable (like OCCT)?

LinX is a front-end for Linpack. With it there's no need to manually configure the startup file for problem size and what not. I like it because unlike some other Linpack utilities floating around it's clean and simple looking. Plus it is easy to update to new binaries when released.

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