Intel Shares GPU, CPU Information at Architecture Day 2020

[Guest_Jim_*]

Today Intel has held its Architecture Day 2020, where it showed off new technologies and details for some of the upcoming products we can expect from the company. Naturally the future of its CPUs were shown but we also got information on the upcoming Intel discrete GPUs, including some that will target gamers. A large part of why Intel has decided to develop its own dedicated GPUs is to sell products for servers, data centers, and supercomputers, but the company also wants to enter the consume space and upset the current duopoly between AMD Radeon and NVIDIA GeForce GPUs.

Looking first at the GPU information, we now know it is the Xe-HPG variant of the Xe graphics IP that will target gamers. Beneath it in the larger Xe stack is Xe-LP, designed for integrated and entry-level situations, and above it the Xe-HP variant for data center and AI use cases. At the top is the Xe-HPC for exascale applications. To serve the high-performance compute market, Intel is applying a number of advanced technologies into Xe-HPC and Xe-HP will take advantage of EMIB to connect the GPU's multiple tiles. For the Xe-HPG and Xe-LP versions though, standard packaging methods will be used. Interestingly, while Xe-LP will be manufactured by Intel, the company has shown Xe-HPG will actually be manufactured on an external process, so we could see coming from TSMC or Samsung nodes, for example. This could mean then that, at least for the first generation of the Intel GPU, it, AMD, and NVIDIA GPUs might all be produced on substantially similar processes. It is expected for Xe-HPG to ship in 2021 and it will feature support for new graphics technology, including ray tracing. Unfortunately it only says 2021, so we do not know when next year we can expect it, but there are plenty of more trade shows before then for such information to be announced.

The advanced technologies Intel is going to use in Xe-HPC include its new 10 nm SuperFin design that incorporates new SuperMIM capacitor and redefined FinFET designs. The new capacitor design enables a five times increase in metal-insulator-metal capacitance and reduces resistance across vias by 30% with a novel thin barrier. The new FinFET design features an improved gate process, additional gate pitch for higher drive current, and enhanced epitaxial source/drain, which should lower resistance and increase strain. Intel is claiming the application of its 10 nm SuperFin technology will grant it a performance improvement comparable to a full-node transition and is the largest single intranode enhancement in the company's history. It will be used in the Xe-LP and for the base tile of the Xe-HPC GPUs. Intel also working on Enhanced SuperFin and it will be used along with EMIB in the Xe-HP GPU and for the Rambo Cache tile in Xe-HPC, which is meant to give cores access to more data. The fourth tile to the Xe-HPC design is the Link I/O tile and it will be produced on an external process, with all four tiles then packaged together using Foveros and Co-EMIB.

Now coming to the CPUs, Tiger Lake, the next-generation mobile processor will be based on the 10 nm SuperFin technology. It is already in production and going to customers with OEM release expected in the holiday season. Tiger Lake will incorporate the Willow Core CPU microarchitecture and Xe graphics with up to 96 execution units. The Willow Cove design should provide large frequency and efficiency improvements, as it is built on the Sunny Cover architecture and will leverage the 10 nm SuperFin technology. It will also introduce a redesigned caching architecture and security enhancements with Intel Control Flow Enforcement Technology. The Tiger Lake design will feature Gaussian Network Accelerator 2.0, enabling low-power neural inferencing compared to running on the CPU, integrated PCIe 4 and ThunderBolt 4/USB 4 for low-latency, high-bandwidth access to memory.

Another technology teased is for chip packaging. Hybrid bonding offers an alternative to the traditional method of bonding in modern packaging technologies, with Intel suggesting it can enable aggressive bump pitches of 10 microns and smaller. For comparison, Intel states standard packaging had a bump pitch of 100 microns and its Foveros technology having a pitch between 50 and 25 microns. By achieving smaller bump pitches, the interconnect between chips can be much denser, enabling greater bandwidth while reducing power requirements. While Foveros enables energy usage of 0.15 pico-Joules per bit, Intel predicts this new technology will enable be less than 0.05 pico-Joules per bit.

Source: Intel

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