Why does my FX60 always fail dual prime?

[thomas hobbes]

While my fx60 is stable in gaming at 2.8GHz it always always fails when i try to test it by running two instances of prime 95, at the exact moment when both cores are fully utilised ie. cpu usage reaches 100%. This happens even when i test it at stock speeds and voltage. Can anyone enlighten me as to why this might be the case?

[Guest caffeinejunkie]

Do you have dual prime set up properly?

[thomas hobbes]

Err I guess not. I will try your link and see how it goes, thanks.

[thomas hobbes]

Right have set up and run dual prime as per your link. Again cpu 0 failed within 1 minute while cpu 1 is merrily priming away. Any other suggestions?

[Guest caffeinejunkie]

core 0 tends to be the weaker core for most people and unfortunently your just simply not fully stable at 2.8ghz

[thomas hobbes]

Thats my point mate. However the same thing happens at stock speeds of 2.6GHz as well.

[Guest caffeinejunkie]

you tried 2.6 again with dual prime properely setup? Try manually setting the vcore to 1.4v in the bios then testing at stock again. Also I dont see how it could casue only core 0 to crash but in some weird way it could be the memory controller so post all of your settings in the DRAM config.

[thomas hobbes]

Ok I tried boosting to 1.4v which seems to have worked wonders as its been priming at 100% at 2.8GHz for about 20 mins now, which I know isnt alot but its significant for me as thats 19 minutes longer than Ive ever had.

 

Here are my DRAM config settings (which were posted by another user on these forums):

 

DRAM Frequency Set - 200=RAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 06 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 10 Bus Clocks

Row refresh cyc time (Trfc) - 15 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3072 Cycles

ODD DIVISOR - Disable

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase

DQS Skew Value - 200

DRAM Drive Strength - Level 5

DRAM Data Drive Strength - Level 1

Max Async Latency - auto

DRAM Response Time - Normal

Read Preamble Time - auto

IdleCycle Limit - 4 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 4 x

Bypass Max - 02 x

32 Byte Granularity - Disable(4 Bursts)

[Guest caffeinejunkie]

wow those are weird timings

 

try these:

 

DRAM Frequency Set - 200=RAM/FSB:1/1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 06 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 12 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 7

DRAM Data Drive Strength - Level 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 6.0 Nano Seconds

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

[thomas hobbes]

Thanks will try them shortly.

[thomas hobbes]

Have been testing the new timings for about 30 mins now. My fingers are firmly crossed. Thanks for the help.

[n00bzor]

I have almost same rig as you. Please see below settings that are rock solid for me at 2.801Ghz. I go back to these settings whenever I want sure-fire stability (I also have these settings saved as my CMOS Bank 1 settings.)

 

I would suggest that you try these, if you are not 8hrs Prime95 stable with your current settings.

 

For Official 406 BIOS (sorry I don't know your BIOS version):

 

Genie BIOS Settings:

 

FSB Bus Frequency - 216

LDT/FSB Frequency Ratio – 4.0

CPU/FSB Frequency Ratio – x 13.0

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value – 1.325v

 

CPU VID Control - 1.425v

CPU VID Special Control - Auto

LDT Voltage Control - 1.20v

Chip Set Voltage Control - 1.50v

DRAM Voltage Control – 2.80v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 (DRAM/FSB:1/01)

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3.0

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 10 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3072 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Auto

DRAM Data Drive Strength - Auto

Max Async Latency – 8.0

DRAM Response Time – Fast

Read Preamble Time – 6.0

IdleCycle Limit - 016 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16x

Bypass Max - 07x

32 Byte Granularity - Disable(4 Bursts)

 

OCDB Benchmarks Passed:

 

CPU-Z: cpu = 2808.1 Mhz

Prime95 x 2 cores = Stable for 8 hours 13 minutes on each core.

3dMark01 = 31499

3dMark03 = 29119

3dMark05 = 13322

3dMark06 = 7741

Everest Memory Read = 4825