Gothic Case Posted July 7, 2006 Posted July 7, 2006 I realized today that my problem is gone for good when I set the AGP BUS Latency to 64 instead of the default (32). But the BIOS option is the AGP Controller latency.... is there any WPCredit way to change the BUS latency?? Thx! Share this post Link to post Share on other sites More sharing options...
charlie22911 Posted July 7, 2006 Posted July 7, 2006 there are several windows tools that will do that without WP credit. nFII tweaker is one of them. its buried in one of these older threads here somewhere... BTW what problem do you speak of? i may set that and see what i get as well. EDIT: here is the thread with the program, http://www.dfi-street.com/forum/showthread...nForce2+Tweaker Share this post Link to post Share on other sites More sharing options...
NEOAethyr Posted July 7, 2006 Posted July 7, 2006 nf2 tweaker was way off. I have'nt worked on these in a long time though. I got more stuff to doit, but have'nt got to it at all. So it is as it is. [COMMENT]=Made by NEOAethyr. [MODEL]=nForce2 Ultra 400 [VID]=10DE:nVidia [DID]=01E8:AGP Bridge ;;;;; Header Region : [bytes : 0h - 39h] [16 Dwords] ;;;; Main Header Region : [bytes : 0h - 15h] [4 Dwords] ;;; 00h ;; Vendor ID Register : [bits : 0 - 15] [Word] [00:7]=Vendor ID (Bits: 8-15) FFFFh=Device Error [00:6]=(Same As Above) [00:5]=(Same As Above) [00:4]=(Same As Above) [00:3]=(Same As Above) [00:2]=(Same As Above) [00:1]=(Same As Above) [00:0]=(Same As Above) [01:7]=Vendor ID (Bits: 0-7) FFFFh=Device Error [01:6]=(Same As Above) [01:5]=(Same As Above) [01:4]=(Same As Above) [01:3]=(Same As Above) [01:2]=(Same As Above) [01:1]=(Same As Above) [01:0]=(Same As Above) ;; ;; Device ID Register : [bits : 16 - 31] [Word] [02:7]=Device ID (Bits: 8-15) [02:6]=(Same As Above) [02:5]=(Same As Above) [02:4]=(Same As Above) [02:3]=(Same As Above) [02:2]=(Same As Above) [02:1]=(Same As Above) [02:0]=(Same As Above) [03:7]=Device ID (Bits: 0-7) [03:6]=(Same As Above) [03:5]=(Same As Above) [03:4]=(Same As Above) [03:3]=(Same As Above) [03:2]=(Same As Above) [03:1]=(Same As Above) [03:0]=(Same As Above) ;; ;;; 04h ;; Command Registers : [bits : 0 - 15] [Word] [04:7]=Address / Data Stepping 1=Wait Cycles Enabled [04:6]=Parity Error Response 0=Disabled 1=Enabled [04:5]=VGA Palette Snoop 0=Disabled 1=Enabled [04:4]=Mem Write&Invalidate CMD 0=Disabled 1=Enabled [04:3]=Special Cycle Recognition0=Disabled 1=Enabled [04:2]=Bus Mastering 0=Disabled 1=Enabled [04:1]=Memory Access 0=Disabled 1=Enabled [04:0]=I/O Access 0=Disabled 1=Enabled [05:1]=Fast BackToBack Cycle 0=Same Only 1=Diff Allow [05:0]=System Error Line (SERR#)0=Disabled 1=Enabled [06:7]=Fast BackToBack Capable 0=No Support 1=Supported [06:6]=User Definable Features 0=No Support 1=Supported [06:5]=66MHz Capable 0=No Support 1=Supported [06:4]=New Capability List 0=No Support 1=Supported ;; ;; Status Registers : [bits : 16 - 31] [byte] [07:7]=Detected Parity Error 0=None 1=Error [07:6]=Signaled SystemError Line0=None 1=Error [07:5]=Received Master Abort 0=None 1=Aborted [07:4]=Received Target Abort 0=None 1=Aborted [07:3]=Signaled Target Abort 0=None 1=Aborted [07:2]=Device Select Timing 10=Slow 11=Unknown [07:1]=01=Medium 00=Fast [07:0]=Data Parity Error 0=None 1=Error Detected ;; ;;; 08h ;; Revision ID Register : [bits : 0 - 7] [byte] [08:7]=Revision ID [08:6]=(Same As Above) [08:5]=(Same As Above) [08:4]=(Same As Above) [08:3]=(Same As Above) [08:2]=(Same As Above) [08:1]=(Same As Above) [08:0]=(Same As Above) ;; ;; Class Code Registers : [bits : 7 - 31] [Word + Byte] [09:7]=Programming Interface [09:6]=(Same As Above) [09:5]=(Same As Above) [09:4]=(Same As Above) [09:3]=(Same As Above) [09:2]=(Same As Above) [09:1]=(Same As Above) [09:0]=(Same As Above) [0A:7]=Sub Class [0A:6]=(Same As Above) [0A:5]=(Same As Above) [0A:4]=(Same As Above) [0A:3]=(Same As Above) [0A:2]=(Same As Above) [0A:1]=(Same As Above) [0A:0]=(Same As Above) [0B:7]=Base Class [0B:6]=(Same As Above) [0B:5]=(Same As Above) [0B:4]=(Same As Above) [0B:3]=(Same As Above) [0B:2]=(Same As Above) [0B:1]=(Same As Above) [0B:0]=(Same As Above) ;; ;;; 0Ch ;; Cache Line Size Register : [bits : 0 - 7] [byte] [0C:7]=Cache Line Size [0C:6]=(Same As Above) [0C:5]=(Same As Above) [0C:4]=(Same As Above) [0C:3]=(Same As Above) [0C:2]=(Same As Above) [0C:1]=(Same As Above) [0C:0]=(Same As Above) ;; ;; Latency Timer Register : [bits : 8 - 15] [byte] [0D:7]=Latency [0D:6]=(Same As Above) [0D:5]=(Same As Above) [0D:4]=(Same As Above) [0D:3]=(Same As Above) ;; ;; Header Type Register : [bits : 16 - 23] [byte] [0E:7]=Header Type [0E:6]=(Same As Above) [0E:5]=(Same As Above) [0E:4]=(Same As Above) [0E:3]=(Same As Above) [0E:2]=(Same As Above) [0E:1]=(Same As Above) [0E:0]=(Same As Above) ;; ;; BIST Registers : [bits : 24 - 31] [byte] [0F:7]=Built In Self Test 0=No Support 1=Supported [0F:6]=Initialize Built In Self Test [0F:3]=Completion Status [0F:2]=(Same As Above) [0F:1]=(Same As Above) [0F:0]=(Same As Above) ;; ;;; ;;;; ;;;; Header Type Dependent Region : [bytes : 16h - 39h] [12 Dwords] ;;;; Header Type : 01h ;;; 10h ;; Base Address Register 0 : [bytes : 10h - 13h] [1 Dword] ;; ;;; 14h ;; Base Address Register 1 : [bytes : 14h - 17h] [1 Dword] ;; ;;; 18h ;; Primary Bus Number Register : [byte : 18h] [1 Byte] ;; ;;; 19h ;; Secondary Bus Number Register : [byte : 19h] [1 Byte] ;; ;;; 1Ah ;; Subordinate Bus Number Regsiter : [byte : 1Ah] [1 Byte] ;; ;;; 1Bh ;; Secondary Latency Timer Regsiter : [byte : 1Bh] [1 Byte] [1B:7]=Secondary Latency Timer [1B:6]=(Same As Above) [1B:5]=(Same As Above) [1B:4]=(Same As Above) [1B:3]=(Same As Above) [1B:2]=(Same As Above) [1B:1]=(Same As Above) [1B:0]=(Same As Above) ;; ;;; ;; I/O Base Register : [byte : 1Ch] [1 Byte] ;; ;;; ;; I/O Limit Register : [byte 1Dh] [1 Byte] ;; ;;; ;; Secondary Status Register : [bytes : 1Eh - 1Fh] [1 Word] [1E:7]=Fast BackToBack Capable 0=No Support 1=Supported [1E:5]=66MHz Capable 0=No Support 1=Supported [1F:7]=Detected Parity Error 0=None 1=Error [1F:6]=Signaled SystemError Line0=None 1=Error [1F:5]=Received Master Abort 0=None 1=Aborted [1F:4]=Received Target Abort 0=None 1=Aborted [1F:3]=Signaled Target Abort 0=None 1=Aborted [1F:2]=DEVSEL# Timing 10=Slow 11=Unknown [1F:1]=01=Medium 00=Fast [1F:0]=Data Parity Error 0=None 1=Error ;; ;;; ;; Memory Base Register : [bytes : 20h - 21h] [1 Word] ;; ;;; ;; Memory Limit Regsiter : [bytes : 22h - 23h] [1 Word] ;; ;;; ;; Prefetchable Memory Base Register : [bytes : 24h - 25h] [1 Word] ;; ;;; ;; Prefetchable Memory Limit Register : [bytes : 26h - 27h] [1 Word] ;; ;;; ;; Prefetchable Base Upper 32 Bits Register : [bytes : 28h - 2Bh] [1 Dword] ;; ;;; ;; Prefetchable Limit Upper 32 Bits Register : [bytes : 2Ch - 2Fh] [1 Dword] ;; ;;; ;; I/O Base Upper 16 Bits Register : [bytes : 30h - 31h] [1 Word] ;; ;;; ;; I/O Base Upper 16 Bits Register : [bytes : 32h - 33h] [1 Word] ;; ;;; ;; Capabilities Pointer Registers : [byte : 34h] [1 Byte] ;; ;;; ;; Reserved : [bytes : 35h - 37h] [1 Word + 1 Byte] ;; ;;; ;; Expansion ROM Address Register : [bytes : 38h - 3Bh] [1 Dword] ;; ;;; ;; Interrupt Line Register : [byte : 3Ch] [1 Byte] ;; ;;; ;; Interrupt Pin Register : [byte : 3Dh] [1 Byte] ;; ;;; ;; Bridge Control Register : [bytes : 3Eh - 3Fh] [1 Word] [3E:7]=Fast Back To Back Enable 0=Disabled 1=Enabled [3E:6]=Secondary Bus Reset [3E:5]=Master Abort Mode [3E:4]=VGA 16Bit Decode [3E:3]=VGA Enable [3E:2]=ISA Enable [3E:1]=SERR# Enable [3E:0]=Parity Error Responce [3F:3]=DiscardTimer SERR# Enable [3F:2]=Discard Timer Status 0=No Error 1=Timed Out [3F:1]=Secondary Discard Timer 0=32768 Clks 1=1024 Clks [3F:0]=Primary Discard Timer 0=32768 Clks 1=1024 Clks ;; ;;; ;;;; ;;;;; ;;;;; Device Dependent Region : [bytes : 40h - FFh] [] Edit: Might as well mention what I got. I got all PCI-SIG docs related to stuff like this. Microsoft src code for pci config space handling. Then for cards themselves, actual code for those nv card's pci config space, older ones but hey(Up to and including the gf3). Which includes scratch as well which is neat... :. Just have'nt had the time. Edit: Messed around a tiny bit and added base class values. Sub clas I don't think I an do with the constraints in wpcredit, it does'nt give me enough room for descriptions. I checked and they are halfway accurate. But..., they need to be worked on more. I prmised to release them quite a while back but never did. Well, I dn if you guys understand why or not, it's because I have to read through a few books and src code to figuer it all out. Then making a pcr file out of them, with corect spacing, best as possioble descriptions within that small confined space, etc. I was wokring on a system where I could copy and past diff portions of headers related to other devices. Making it the end all pcr thihng I dn whqat to call it. So I could copy portions out and have them 100% accurate depending on the device. And clean. I hav'nt re-checked the mem controller or anythign like that though in some time, so... That sort of stuff me be half @ssed right now. Plus there was stuff I need to check on this asus I got to the side. I need to make dumps of it for more reg's, because it's got bios options this lpb don't have. Blah blah blah blah. I'll attach them anyways, only my nvidia ones. The 00F1h one is another half @ssed one. I never did work on that one very hard, nor very long. Some of the stuff I guessed... I can add power states to all devices later using this src code from ms I got. Oops, one small typo in the base class, ohwell for now. Also there's min grant and max latency in the nb and one of the mem controllers, they probably don't belong there. Share this post Link to post Share on other sites More sharing options...
NEOAethyr Posted July 7, 2006 Posted July 7, 2006 Gothic Case All video card on the nv chipset do 00h latency best. However some cards have a slow as heck bios, like the 6600gt's. So by default, they have a hard time handling it. When they are working right however, the best value for the bios ver of the latency, 0dh btw, is 0. On via chipsets I think it was 38h or 40h was optimal, for both ati and nv cards, I tested them... Share this post Link to post Share on other sites More sharing options...
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