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SLI-D memory help


Maec

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Evening guys. got her up and runing fine at 200 FSB Freq. But when I climbed up to just 220, Im getting errors in OCCT. As this is such a low OC Im wondering where to go next.

Using Thunda's OC guide I first dropped the Dram Freq to 100 1/02 and the cpu will clock to 2900 and easily runOCCT, then Prime for 10 hours. But as soon as I go back and bring the Dram to 200 1/01 I run into problems.

 

I'm still trying to wrap my head around all the information and some help would be appriciated. I tried it with the 180 divider too but had the same problem. I would like to hit my max at 1:01 for now though and get a baseline for stability before I start using the divider to get the CPU up towards 2.7+

 

I didnt want to push my luck copying the bios from the OC gallery yet, but I have looked through it. I cant see where my machine differs (besides the obvious all parts are not created equally) from what some of the other folks are running.

 

Runing plenty cool too btw. CPU under load around 40c

 

 

--------------------------------------------------------------------------------

 

DFI LANPARTY nF4 SLI-D 3/10 bios ( havent touched them )

 

AMD Athlon 64 3700+ San Diego Socket 939 Processor

 

OCZ Gold Series 1GB (2 x 512MB) OCZ4001024ELDCGE-K

 

1 BFG 6600GT OC 128mb Driver ver. 6.6.9.3 (from DFI cd, good for now)

 

1 IBM 60GB IDE drive (good for now)

 

Sony DVD drive

 

ENERMAX All in One Noisetaker Series EG701AX-VE SFMA(24P) ATX12V 600W

 

Thermalright XP-120 aluminum heatpipe heatsink + Panaflow 120mm fan

 

 

 

==========

 

 

Genie BIOS Settings:

 

FSB Bus Frequency - 220

LDT/FSB Frequency Ration - x4

CPU/FSB Frequency Ratio - x11.0

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - StartUp

 

CPU VID Control - 1.425v

CPU VID Special Control - Avove VID * 110%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.70v

DRAM Voltage Control - 3.00v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 (DRAM/FSB:1/01)

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.0

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 07 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Disnabled

 

 

 

DQS Skew Control - Increase Skew

DQS Skew Value - 0

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 2

Max Async Latency - 07.0

Read Preamble Time - 05.0

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(8 Bursts)

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