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Guest burningrave101_merged

OCZ PC3200 Platinum Rev2 + Venice/San Diego

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Guest burningrave101

Anyone who has OCZ PC3200 Platinum Rev2 and a new Venice or San Diego core post your BIOS settings. Me and alot of other people have been trouble getting the two to play well together because of most likely a weak memory controller. I'm going to try some new settings that i just saw another user using and then i'll post mine. This will help those of us who are having problems as to which settings we should try to get stable, especially at higher clock speeds at 1:1.

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Guest burningrave101

I dont have a problem getting it stable at stock speeds, i'm just not able to overclock very well at 1:1 1T. I have to use a divider and disable CMD in order to get my CPU to 2800Mhz.

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Guest burningrave101

I just tried the settings posted by MarcusOCZ and it booted into windows at 280Mhz but it was only Prime95 stable for around 6 minutes. This is really starting to get irritating because there just too many options and too many different combinations that even a single DRAM setting can totally crash stability.

 

http://www.bleedinedge.com/forum/showthrea...91965#post91965

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Guest burningrave101

I just flashed to the 510-2 beta BIOS since several people have been suggesting it and right now i'm testing MarcusOCZ's DRAM settings at 280Mhz with 2.7v and the system has been Prime95 stable for several minutes now. If it remains stable then i'll do some more fine tuning of the settings to see where i can improve performance and remain stable.

 

These are my current settings:

 

200

Enable

2.5

4

7

3

7

16

3

3

2

3

4708

Auto

Disabled

Auto

0

Auto

Auto

Auto

Auto

64

Disable

16X

7X

Disable

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Guest burningrave101

I'm running the 510-3 BIOS now and these are my current settings i'm trying. Their not Prime stable but i'm trying to get there by tweaking a little bit at a time.

 

HTT = 280Mhz

vDDR = 2.93v

 

DRAM Frequency Set: 200 (DRAM/FSB:1/01)

Command Per Clock (CPC): Enabled

CAS Latency Control (Tcl): 2.5

RAS# to CAS# delay (Trcd): 03 Bus Clocks

Min RAS# active time (tras): 07 Bus Clocks

Row Percentage Time (Trp): 03 Bus Clocks

Row Cycle Time (Trc): 10 Bus Clocks

Row refresh cyc Time (Trfc): 14 Bus Clocks

Row to Row delay (Trrd): 3

Write recovery time (Twr): 3

Write to read delay (Twtr): 2

Read to Write delay (Trwt): 3

Refresh Period (Tref): 2336

Write CAS Latency (Twcl): 1

DRAM Bank Interleave: Enabled

DQS Skew Control: Auto

DQS Skew Value: 0

DRAM Drive Strength: Level 8

DRAM Data Drive Strength: Level 3

Max Async Latency: 8x

Read Preamble Time: 5x

IdleCycle Limit: 256 Cycles

Dynamic Counter: Enabled

R/W Queue Bypass: 16x

Bypass Max: 07x

32 Byte Granularity: Disable(8 Bursts)

 

If anyone else has a Venice or San Diego and TCCD/TCC5 could you PLEASE post your DRAM settings as well so we could all try to figure out what settings to adjust to get better stability at higher clocks?

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you would had to go to cl-2.5-4-3-7 if needed.....try below 1st.

 

try drive strength to 7 and data drive strength to 2

fix that and try memtest 5 and 8 loop...

 

adjust vdimm up or down to see whether errors gone or not...

increase read preamble time to 5.5 if needed

trwt can increase by 1 if needed...

 

with -3 bios,my tccd like voltage.....with -1...it can't go pass 2.8v else errors..

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If you are looking for simply stock settings to get stable first. I was able to prime for 8 hours on this:

 

200 (1/1)

enable

2

2

7

2

7

14

5

4

3

5

3120

05

enable

 

increase

0

7

4

7

5

256

disable

16

7

disable(8 bursts)

 

Again, this was just at stock speed, FSB 200.

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Guest burningrave101

I'm looking to try and run 280Mhz 1:1. I've tried running dividers but the dividers dont seem to be very stable for me ither.

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