NF4 tRef: the definitive answer?

[ether.real]

To be more accurate about what Tref does, at every interval of Tref, the memory is read by the logic drivers and then re-written. Not a pulse of electricity. If Tref is set too high, some cells may lose their data (from not being refreshed fast enough) and errors will become evident. This gets worse with higher clocks and heat (usually).

[Dracula]

1. The BEST thing to do is to let your RAM find its own path by setting the tREF to "AUTO" in your DRAM Configuration Settings in your BIOS.

2. Log back in to your OS and use some program like A64 Tweaker v0.60, as just one example, to observe what the native refresh rate (i.e. - 200MHz 3.9µs) of your memory is.

3. Use the charts at these links (the charts are located about midway down on the middle of the page) http://www.dfi-street.com/forum/showpost.p...37&postcount=10 and http://forums.extremeoverclocking.com/show...ad.php?t=170999 to determine the cycles.

4. Using this information, go back into your BIOS and set your tREF to that setting for your cycles.

 

 

The tREF is defined as the number of clock cycles between refreshes, or the duration of the pause between each actual refresh. The MHz and the µs portion of the tREF have to do with the actual refresh itself. Just so everyone is clear on this point, when you set the tREF to auto in your BIOS, the measurement in MHz for the tREF is, of course, the amount of natural/native data bandwidth (or frequency) which all the chips on your memory's PCB (Printed Circuit Board) can handle (internally flash) in a given period of time in order to keep the temporary data stored by your RAM, updated. Think of it like hitting the F5 key on your keyboard to refresh the screen (And for all you “picky-people”, I am using this as an example only. It is obviously not the same exact thing). When you hit F5 a certain amount of data will be refreshed in a certain period of time. The other number to the right of the MHz, the µs (which is not the letters “u” and “s”, but is rather a symbol that denotes a measurement in microseconds or One-Millionth of a second), is that preset given period of time allotted to the memory to refresh that amount of data bandwidth.

 

 

In summation, where 3120 = 200MHz(15.6µs) [NOTE: this is not an actual equation]:

 

1. The 3120 value represents the delay (in clock cycles) between each refresh.

2. The 200MHz value pertains to the actual refresh and represents the amount of data bandwidth that will be updated during each actual refresh.

3. And the 15.6µs value also pertains to the actual refresh and represents the amount of time (measured in microseconds) that will be taken to refresh the 200MHz of data bandwidth.

 

*** 200MHz of data bandwidth will be refreshed in a 15.6 microsecond period of time, continually, with 3120 clocks of delay between each of those refreshes.

 

 

JSYK and FYI, the comment, “The ram needs to be refreshed at 7.8us... PERIOD” is completely wrong! What he is referring to is the refresh rate of the RAM's interface between itself and the motherboard's DIMM slot, or you can refer to it as an external interface refresh-rate (kind of like the interface bandwidth on a hard drive). The tREF in your BIOS is the RAM's internal refresh-rate. Most, though not all, high-end memory sticks natively run at and are most stable when fixed to a tREF with a 3.9µs setting. Remember to set your tREF to auto in the beginning; let your RAM find its own path and then go from there.

-------------------------------------------------------------------------------------------------------------------------------------------------

:cool:

DRACULA

• MoBo

= DFI LANPARTY nF4 SLI-DR

• CPU

= FX-57 (90nm

process, San Diego core

) [ADAFX57BNBOX]

• Memory

= 1GB of OCZ Technology (1T

Mode

), EL DDR PC-4800 Dual Channel Platinum Elite Edition (

hand-picked,

100%

TCCD

chips

), Qt.2 [OCZ6001024EEPE-K]

• Hard Drives

=

a)

74GB WD Raptor, Qt.4 [WD740GD]

B)

500GB Hitachi Deskstar 7K500 SATA II, Qt.4 [0A31619] *** Total SATA Storage:

2.296

Terabytes

***

• BIOS

= 702-2 with Change-Log Update

• OS

= Windows XP Pro SP2

and

Windows XP Pro x64-bit

• Video Card

(

single card,

non

-

SLI Mode

) = BFG GeForce 6800 Ultra OC™ PCIe 512MB GDDR3/TV-Out/Dual-DVI (

Retail Box

) [bFGR68512UOCX]

• Video Driver

(

nVIDIA

) = ForceWare v77.77 (

non

-Beta

)

• Monitor

= ViewSonic VP191

b

(

new

8ms

revision

)

• Optical Drives

= ASUS DRW-1608p, Qt.2 [DRW1608P]

• Case

= Aspire X-Navigator, mid-Tower [ATXA8NW-BK]

• Cooling

(

air only

) =

a)

Thermalright XP-90C Heat-Sink

B)

92mm Vantec Tornado (119

CFM

- 4800

RPM

's - 56.4

dBA

) CPU Fan [TD9238H]

c)

Arctic Silver 5 compound

• PSU

= Thermaltake,

680

Watts

, SLI-ready [W0049]

• Audio

= Creative Labs, GigaWorks S750 (

700

Watts

,

7.1

Channel

Speaker System – Retail

) [51MF7010AA000]

[ether.real]

very nice information, thanks!

[DeepBlue]

...

The tREF is defined as the number of clock cycles between refreshes, or the duration of the pause between each actual refresh. The MHz and the µs portion of the tREF have to do with the actual refresh itself. Just so everyone is clear on this point, when you set the tREF to auto in your BIOS, the measurement in MHz for the tREF is, of course, the amount of natural/native bandwidth (or frequency) which all the chips on your memory's PCB (Printed Circuit Board) can handle (internally flash) in a given period of time in order to keep the temporary data stored by your RAM, updated. Think of it like hitting the F5 key on your keyboard to refresh the screen (And for all you “picky-people”, I am using this as an example only. It is obviously not the same exact thing). When you hit F5 a certain amount of data will be refreshed in a certain period of time. The other number to the right of the MHz, the µs (which is not the letters “u” and “s”, but is rather a symbol that denotes a measurement in microseconds or one millionth (10-6) of a second), is that preset given period of time allotted to the memory to refresh that amount of bandwidth.

 

 

In summation, where 3120 = 200MHz(15.6µs):

 

1. The 3120 value represents the delay (in clock cycles) between each refresh.

2. The 200MHz value pertains to the actual refresh and represents the amount of data bandwidth that will be updated during each actual refresh.

3. And the 15.6µs value also pertains to the actual refresh and represents the amount of time (measured in microseconds) that will be taken to refresh 200MHz of data bandwidth.

 

*** 200MHz of bandwidth will be refreshed in a 15.6 microsecond period of time, continually, with 3120 clocks of delay between each of those refreshes.

 

 

JSYK and FYI, the comment, “The ram needs to be refreshed at 7.8us... PERIOD” is completely wrong! Most, not all, high-end memory sticks natively run at and are most stable when set to a tREF with a 3.9µs.

 

Right info.

 

And about your last paragraph, the best is to have an utility which reads dimm's tref from SPD like rightmark memory analizer whch tells you that so that you can calculate tref for the target speed you will be using.

 

It's not absolute for every dram speed, as here states a fragment of amd's 26094.pdf file called "bios and kernel developer's guide for athlon 64 and opteron processors"

 

4.1.1.8 tREF (Refresh Rate)

 

The tREF is not an SPD ROM parameter but a field that the DRAM controller requires and that can be obtained from several bytes in the SPD ROM. Typically, the entire DRAM must have every row refreshed at least once every 64 ms. The average time between two row refreshes is thus based on the number of rows in the DRAM and the clock frequency.

 

The clock frequency was previously derived. The number of rows in the implementation can be read

from SPD byte 3. This provides the number of row address bits for each of the two possible chip

selects on a DIMM. (Note that each chip-select range of a two chip-select DIMM uses devices that

have the same number of rows). A design with 12 row address bits implies 4k rows per internal

device chip select. This maps to a refresh every 15.6 µs on average. There are also 8k (13 row address

bits) and 16k (14 row address bits) row devices. By knowing the number of rows and the frequency,

the DRAM controller configuration register can be correctly programmed. All 4k row devices require

an average refresh interval of 15.6 µs and all 8k and 16k row devices require a 7.8 µs average refresh

interval.

[ojon]

Guys,

 

Angry reminded me that Oskar Wu recommended setting Tref at AUTO.

He reminded me that Oskar is the board's designer. So AUTO it is for me!

 

Ojon

[cantankerous]

but what does AUTO default to?

[DeepBlue]

but what does AUTO default to?

 

I don't really know

 

We should ask Oskar Wu about that

[Lane]

There's a thread on DFI for memory settings about the memory guide you will find the Tref you can read on A64 tweakers,( example: 200,7.8ns) and the report in number you have in bios. http://www.dfi-street.com/forum/showthread.php?t=11397

 

Personally i need actually use asynchro speed on my FSB and DDR Speed, so i use

166Mhz, my spread on everset give 7.8ns... I read the good line: -1168 need set in bios. It's not the same give by auto, it try using a 166Mhz,3.9ns and this give me real instability...

 

At 1168 i can then tweak easy other latency time for tighter my setting... 1Hour Primetest pass, SuperPI 1-2-4-8-16Mo without break, no errors.

[LlamaOfDoom]

OH GOD! What have I done to deserve this?

 

OK, so what is the best procedure? Just set it on auto and leave it there?

Run some little formula after getting our value from A64tweaker, then plug our value in?

Leave it on auto?

FYI: I am running:

305FSB

4:3

229MHz DRAM

Currently Tref is set to 0648 or "166MHz 15.6us"

Running 2x512MB XMS3500C2 BH-5

 

Regards, Anthony Hunt

[uwackme]

My max results with BH5 and UTT-CH are at 1560 or 3120. Stick to one of them, they are basically a tie, 3120 will refresh less often, if you have stability issues switch to 1560.

[Dracula]

About 3 weeks ago I created an easy-to-read, COMPLETE tREF table, in color, but I don't know how to get it posted here at DFI-Street. JSYK, each tREF setting in A64 Tweaker has two refresh-delay settings in your BIOS (e.g. - 166MHz at 3.9µs can have a refresh delay, in your BIOS, of 1296 or 2560 - so 1296 is faster and more aggressive than 2560. Thereby, the lower the the refresh-delay number, the faster and more aggressive the overall refresh-timings will be...the same goes for higher refresh-data-bandwidths, MHz). Setting your tREF to auto is the safest and most stable thing you can do. As for higher raw-data-bandwidths, on the other hand, there are the aggressive "0032" and "0064" tREF settings in your BIOS {which are not 200MHz(?.?us)}. A tREF of 0032 is a 1.95µs (1.95 microseconds) "snapshot-refresh" of 200MHz of data-bandwidth, punctuated with brief pauses that are 32 clock-periods long. And a tREF of 0064 is a 7.8µs (7.8 microseconds) "snapshot-refresh" of 200MHz of data-bandwidth, punctuated with brief pauses that are 64 clock-periods long.. A tREF of 0016 is the most aggressive setting for "data-bandwidth" (0016 has nearly 150% of the bandwidth of the sum of all the other settings combined - it is also the most sloppy, inefficient and one of the most unstable settings of them all). Typically, it just plain doesn't work because a refresh-delay of 16 Ticks (Ticks = Clock-Cycles or Clocks) is simply too brief to be properly interpreted by most systems (unless your whole system is comprised entirely of "Flag-Ship" components). About my color table, can someone here please give me some helpful advice on posting it, so I can give everyone at DFI-Street ALL of these settings? Thank you!

 

 

MY TOP 5 tREF RECOMMENDATIONS:

 

I recommend not using tREF settings below 200 clock-cycles (unless you possess a "primo" rig), as they are much more unstable and may cause problems for your system. The tREF setting of "auto" is what I suggest the most for overall stable performance. Below, I have listed some good "non-auto" settings that should be stable and improve data-bandwidth:

 

• 0388=100MHz(15.6µs) - STABILITY [5th], Performance/Data-Bandwidth Level [2nd]
  

• 0516=133MHz(15.6µs) - STABILITY [4th], Performance/Data-Bandwidth Level [1st]
  

• 0780=200MHz(15.6µs) - STABILITY [3rd], Performance/Data-Bandwidth Level [3rd]
  

• 1560=200MHz(3.9µs) - STABILITY [2nd], Performance/Data-Bandwidth Level [4th]
  

• 3072=200MHz(3.9µs) - STABILITY [1st], Performance/Data-Bandwidth Level [5th]
  

-------------------------------------------------------------------------------------------------------------------------------------------------

:cool:

DRACULA

• MoBo

= DFI LANPARTY nF4 SLI-DR

• CPU

= FX-57 (90nm

process, San Diego core

) [ADAFX57BNBOX]

• Memory

= 1GB of OCZ Technology (1T

Mode

), EL DDR PC-4800 Dual Channel Platinum Elite Edition (

hand-picked,

100%

TCCD

chips

), Qt.2 [OCZ6001024EEPE-K]

• Hard Drives

=

a)

74GB WD Raptor, Qt.4 [WD740GD]

B)

500GB Hitachi Deskstar 7K500 SATA II, Qt.4 [0A31619] *** Total SATA Storage:

2.296

Terabytes

***

• BIOS

= 702-2 with Change-Log Update

• OS

= Windows XP Pro SP2

and

Windows XP Pro x64-bit

• Video Card

(

single card,

non

-

SLI Mode

) = BFG GeForce 6800 Ultra OC™ PCIe 512MB GDDR3/TV-Out/Dual-DVI (

Retail Box

) [bFGR68512UOCX]

• Video Driver

(

nVIDIA

) = ForceWare v77.77 (

non

-Beta

)

• Monitor

= ViewSonic VP191

b

(

new

8ms

revision

)

• Optical Drives

= ASUS DRW-1608p, Qt.2 [DRW1608P]

• Case

= Aspire X-Navigator, mid-Tower [ATXA8NW-BK]

• Cooling

(

air only

) =

a)

Thermalright XP-90C Heat-Sink

B)

92mm Vantec Tornado (119

CFM

- 4800

RPM

's - 56.4

dBA

) CPU Fan [TD9238H]

c)

Arctic Silver 5 compound

• PSU

= Thermaltake,

680

Watts

, SLI-ready [W0049]

• Audio

= Creative Labs, GigaWorks S750 (

700

Watts

,

7.1

Channel

Speaker System – Retail

) [51MF7010AA000]

[rhiridflaidd]

Sorry to be thick here- but I haven't quite got it.

 

Is there any chance of anybody showing a "worked example" of how they'd tweak their Tref.

 

My tref is 0388 - which seems to break all the rules mentioned here; but seems to keep my ballistix stable at 260mhz. But I can't get any dividers to work. Would my tref value explain why I can't use dividers.