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DFI LANPARTY nF4 SLI-DR - 7/04-2 BigToe BIOS

 

AMD Athlon64 FX-55 San Diego

 

2x512MB Geil One (BH-5)

 

2xEVGA 6800GT 256MB, 430/1.15 81.82 drivers

 

2x74GB Raptors

 

Enermax 600W SLI Ready - Retail

 

 

 

 

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 245

LDT/FSB Frequency Ratio - AUTO

CPU/FSB Frequency Ratio - 12

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.500v

 

CPU VID Control - 1.425

CPU VID Special Control - Above VID * 110%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 3.00v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200=RAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.0

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 05 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 12 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3210 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Auto

DRAM Data Drive Strength - Auto

Max Async Latency - Auto

DRAM Response Time - Fast

Read Preamble Time - Auto

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

http://i10.photobucket.com/albums/a142/oli...rk01Everest.jpg

 

3DMark03:

3dmark03.jpg

 

 

3DMark05:

3dmark05.jpg

 

 

Aquamark 3d:

Aquamark.jpg

 

 

 

==========

 

 

 

short description:

245x12 @ 2940Mhz, 1.425v + 110%

2-2-5-2 @ 3.0v vdimm

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DFI LANPARTY nF4 SLI-DR - 7/04-2 BigToe BIOS

 

AMD Athlon64 FX-55 San Diego

 

2x512MB Geil One BH-5 (GOW1GB3200DC)

 

2xEVGA 6800GT 256MB, 430/1.15 81.82 drivers

 

2x74GB Raptors

 

Enermax 600W SLI Ready - Retail

 

 

 

 

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 297

LDT/FSB Frequency Ratio - AUTO

CPU/FSB Frequency Ratio - 10

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.500v

 

CPU VID Control - 1.425

CPU VID Special Control - Above VID * 110%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 3.10v

 

DRAM Configuration Settings:

DRAM Frequency Set - 166=RAM/FSB:05/06

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.0

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 05 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 7 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3210 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Auto

DRAM Data Drive Strength - Auto

Max Async Latency - Auto

DRAM Response Time - Fast

Read Preamble Time - Auto

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

http://i10.photobucket.com/albums/a142/oli...Li/benchies.jpg

 

3DMark03:

3DMark03.jpg

 

3DMark05:

3DMark05.jpg

 

Aquamark 3d:

AquaMark.jpg

 

Everest Write/Latency:

1a596ad4.jpg

 

==========

 

 

 

short description:

297x10 @ 2970Mhz, 1.425v + 110%

2-2-5-2 @ 3.1v vdimm

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LanParty UT RDX200 CF-DR - 10/11/05 BIOS

 

AMD Athlon 3700+ San Diego IHS Removed Stepping CABGE 0518UPAW

 

Patriot PC3200+ XBLK 512X2 (tccd) (2/4 Orange)

 

Gigabyte 6600GT 128mb 530/1060 81.85

 

2X Hitachi Deskstar SATA II 80g 8m buffer RAID 0

 

NEC ND-3520A DVD-RRW

 

Enermax EG701AX-VE SFMA 600W

 

Thermalright XP-90

 

 

Genie BIOS Settings:

 

FSB Bus Frequency - 270

HT PLL High Speed - Disabled

LDT/FSB Frequency Ratio - x 3.0

CPU/FSB Frequency Ratio - x 10.0

CPU VID StartUp Value - 1.450v

NB-SB Port Configuration - Enhanced

CPU VID Control - 1.500v

CPU VID Special Control - Above VID * 109.6%

DRAM Voltage Control - 3.04v

SB PCIE Voltage - 1.8v

NB Analog Voltage - 1.3v

LDT Bus Voltage - 1.3v

NB Core Voltage - 1.3v

 

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200=RAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl - 2.5

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 07 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 08 Bus Clocks

Row refresh cyc time (Trfc) - 13 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 01 Bus Clocks

Read to Write delay (Trwt) - 02 Bus Clocks

Refresh Period (Tref) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 7

DRAM Data Drive Strength - Level 2

Max Async Latency - 7.0 ns

Read Preamble Time - 5.5ns

IdleCycle Limit - 256 Cycles

Dynamic Counter - Auto

R/W Queue Bypass - 16x

Bypass Max - 04x

32 Byte Granularity - Enable(4 Bursts)

 

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

270x102kr.th.jpg

 

 

3dMark2003:

 

3dm03270x105ch.th.jpg

 

 

3dMark2005:

 

3dm05270x105hb.th.jpg

 

 

Aquamark 3d:

 

am3270x108su.th.jpg

 

Everest Write:

 

ewrite270x106ul.th.jpg

 

Everest Latency:

 

elatency270x100oh.th.jpg

 

Sandra:

 

sandra270x104an.th.jpg

 

==========

 

 

 

short description:

10 x 270 @ 2700Mhz 1.500v + 109.6%

2.5-3-7-3 1:1 @ 3.04v vdimm

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DFI LANPARTY RDX200 CF-DR (10/26/2005 BIOS)

 

AMD Athlon64 4000+ San Diego 1MB L2

 

2x1024MB PC4000 Crucial Ballistix

 

XFX GeForce 7800GT, 490/1310 81.85 drivers

 

160GB Maxtor IDE

 

NEC 3540A Black IDE DVD-RW Drive

 

Seasonic S12-600 (revA2) ATX 600W Power Supply - Retail

 

 

 

*

*

 

rdx_ballistix_270x10_bios-1.jpg

 

rdx_ballistix_270x10_bios-2.jpg

 

rdx_ballistix_270x10_bios-3.jpg

 

rdx_ballistix_270x10_bios-4.jpg

 

*

*

 

==========

 

[b]Genie BIOS Settings:[/b]

[color=red]

FSB Bus Frequency.............................  -  270

HT PLL High Speed.............................  -  Enabled

LDT/FSB Frequency Ratio.......................  -  x 3.0

CPU/FSB Frequency Ratio.......................  -  x 10.0



CPU VID StartUp Value.........................  -  1.500v



NB-SB Port Configuration......................  -  Enhanced



CPU VID Control...............................  -  1.400v

CPU VID Special Control.......................  -  Above VID * 107.2%

DRAM Voltage Control..........................  -  2.70v

SB PCIE Voltage...............................  -  1.8v

NB Analog Voltage.............................  -  1.3v

LDT Bus Voltage...............................  -  1.3v 

NB Core Voltage...............................  -  1.3v

[/color]



[b]DRAM Configuration Settings:[/b]

[color=red]

DRAM Frequency Set............................  -  200=RAM/FSB:01/01

Command Per Clock (CPC).......................  -  Enable

CAS Latency Control (Tcl).....................  -  3.0

RAS# to CAS# delay (Trcd).....................  -  03 Bus Clocks

Min RAS# active time (Tras)...................  -  08 Bus Clocks

Row precharge time (Trp)......................  -  03 Bus Clocks

Row Cycle time (Trc)..........................  -  AUTO

Row refresh cyc time (Trfc)...................  -  AUTO

Row to Row delay (Trrd).......................  -  AUTO

Write recovery time (Twr).....................  -  AUTO

Write to Read delay (Twtr)....................  -  AUTO

Read to Write delay (Trwt)....................  -  AUTO

Refresh Period (Tref).........................  -  AUTO

DRAM Bank Interleave..........................  -  Enabled



DQS Skew Control..............................  -  Auto

DQS Skew Value................................  -  0

DRAM Drive Strength...........................  -  AUTO

DRAM Data Drive Strength......................  -  AUTO

Max Async Latency.............................  -  AUTO

DRAM Response Time............................  -  AUTO

Read Preamble Time............................  -  Auto

IdleCycle Limit...............................  -  AUTO

Dynamic Counter...............................  -  AUTO

R/W Queue Bypass..............................  -  AUTO

Bypass Max....................................  -  AUTO

32 Byte Granularity...........................  -  AUTO

[/color]

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

http://www.angrygames.com/ocdb/angry/rdx20...ix_270x10-1.gif

 

 

3dMark2003:

 

rdx_ballistix_270x10-2.gif

 

 

3dMark2005:

 

rdx_ballistix_270x10-3.gif

 

 

Aquamark 3d:

 

rdx_ballistix_270x10-4.gif

 

 

Everest Memory Writes:

 

rdx_ballistix_270x10-5.gif

 

 

Everest Latency:

 

rdx_ballistix_270x10-6.gif

 

 

==========

 

 

 

short description:

270x10 @ 2700Mhz, 1.400v + 107.2%

3.0-3-8-3 @ 2.70v vdimm

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DFI nF4 DAGF - 08/11/2005 BIOS

 

3200 Venice 0515

 

2x1024mb Patriot LL's

 

Power Color x850xt @ 580621 with Cat 5.10

 

1x 20gig Western Digital IDE drive

 

ASUS IDE CD-ROM Drive

 

OCZ 600w Power Stream SLI Edition

 

Thermalright SLK948U with 92mm Panaflo

 

*

*

*

*

 

==========

 

 

Genie BIOS Settings:

CPU Frequency - 276

Hammer Fid Control - 10

HTT Frequency - 3

PCIE Clock - 100Mhz

 

DDR Voltage Control - 2.7v

Chip Voltage Control - 1.6v

CPU Voltage - 1.60

 

DRAM Configuration Settings:

Mem Clock mode - Limit

Mem Clock Index Value - 166

CAS Latency Control (Tcl) - 2.5

Min RAS# active time (Tras) - 05 Bus Clocks

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Row Cycle time (Trc) - 08 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 01 Bus Clocks

Read to Write delay (Trwt) - 02 Bus Clocks

Refresh Period (Tref) - Auto

Write CAS Latency (Twcl) - Auto

DDR Output Driving - Auto

DDR DQ Drive Strenth - Auto

Bottom of 32Bit[31:24]IO - B0

1T2T Memory Timing - 1T

Read Preamble Value - 5.5ns

Async Latency Value - 8ns

Dynamic IdleCycle Counter - Auto

DRAM Bank Interleave - Enable

Burst Length - 4 beats

Enable ALL DIMM Clock - enable

SW Memory hole remapping - disable

HW Memory hole remapping - disable

MTRR Mapping mode - continuous

DRAM ECC Feature Control - disable

 

 

 

==========

 

 

Prime95 + 3dMark2001SE + 2xCPU-Z :

 

http://img283.imageshack.us/img283/9951/untitled0gb.jpg

 

 

3dMark2003 + Everest Latency :

 

untitled23gz.jpg

 

 

3dMark2005 + Everest Reads :

 

untitled39re.jpg

 

 

Aquamark 3d:

 

untitled46ez.jpg

 

 

==========

 

 

 

short description:

276x10=2760mhz 1.6vcore 2.7vdimm

Mem @ 230mhz 2.5-5-3-2

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DFI LANPARTY nF4 SLI-DR - 7/04-3 BIOS

 

AMD Athlon64 3800+ Manchester X2 CCBWE 0528MPMW

 

2x512MB Patriot XBL PC3200 (tccd)

 

BFG 7800GT OC 256MB, 490/1200 Forceware 81.85 drivers

 

WD740 Raptor

Seagate Barracuda 250G 7200.7

 

Antec Neo Power 480

 

Zalman CNPS9500

 

 

Genie BIOS Settings:

FSB Bus Frequency - 265

LDT/FSB Frequency Ratio - AUTO

CPU/FSB Frequency Ratio - 10.0

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - Startup

 

CPU VID Control - 1.475v

CPU VID Special Control - Above VID * 110%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 2.70v

 

DRAM Configuration Settings:

DRAM Frequency Set - 180=RAM/FSB:09/10

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 07 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 13 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 04 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - 05

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase

DQS Skew Value - 0

DRAM Drive Strength - Level 7

DRAM Data Drive Strength - Level 3

Max Async Latency - 7.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 5.0 Nano Seconds

IdleCycle Limit - 256 Cycles

Dynamic Counter - Enable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

265x10medium0fm.th.png

 

 

3dMark2003:

 

03largesmall7ec.th.png

 

 

3dMark2005:

 

05small1wx.th.png

 

 

Aquamark 3d:

 

265x10aquamark7tc.png

 

 

==========

 

 

 

short description:

265x10 @ 2650Mhz, 1.475v + 110%

2.5-3-7-3 @ 2.70v vdimm

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DFI LANPARTY nF4 SLi-DR - 7/04-22V6 BigToe BIOS

 

AMD Athlon64 3500+ Venice

 

2x512MB GeiL ONE S (TCCD)

 

Leadtek Winfast PX7800GTX TDH, 490/1300 81.85 Forceware

 

Maxtor 78Gig IDE 7200RPM - from old pc

 

Sony CD-RW - from old pc

 

OCZ PowerStream OCZ520ADJSLI ATX 520W Power Supply

 

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 273

LDT/FSB Frequency Ratio - 3x

CPU/FSB Frequency Ratio - 10x

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - Startup

 

CPU VID Control - 1.400v

CPU VID Special Control - Above VID * 113%

LDT Voltage Control - 1.20v

Chip Set Voltage Control - 1.50v

DRAM Voltage Control - 2.7v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200=RAM/FSB:1/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 06 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 17 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 4708 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 5

DRAM Data Drive Strength - Level 1

Max Async Latency - Auto

DRAM Response Time - Fast

Read Preamble Time - Auto

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.3:

 

http://img.photobucket.com/albums/v362/pea...screen1copy.jpg

 

 

3dMark2003:

 

3dmark03.jpg

 

 

3dMark2005:

 

3dmark05.jpg

 

 

Aquamark 3d + Everest Home Edition:

 

http://img.photobucket.com/albums/v362/pea...markeverest.jpg

 

 

==========

 

 

 

short description:

273x10 @ 2730Mhz, 1.400v + 113%

2.5-3-6-3 @ 2.7v vdimm

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DFI LanParty NF4 UT SLI-DR, BIOS 6/23/2005-3

 

AMD AthlonX2 3800+ Manchester, (E4)

 

2x1024MB Crucial Balistix (Z503)

 

Leadtek 6600GT 128MB, 500/1000 81.85 drivers

 

Western Digital Raptor 74GB SATA hdd (8MB cache)

 

Lite-On 1653S CD-ROM Drive

 

PC Power and Cooling Turbo Cool 510 SLI ATX 510W Power Supply

 

Prometia Mach I Phase Change

 

 

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 270

LDT/FSB Frequency Ratio - AUTO

CPU/FSB Frequency Ratio - X 10.0

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.500v

 

CPU VID Control - 1.500v

CPU VID Special Control - Above VID * 110%

LDT Voltage Control - 1.20v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 2.70v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200=RAM/FSB:1/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3.0

RAS# to CAS# delay (Trcd) - 03 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 10 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - Auto

Write CAS Latency (Twcl) - 01 Bus Clock

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase Skew

DQS Skew Value - 255

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 3

Max Async Latency - 7.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 4.0 Nano Seconds

IdleCycle Limit - 016 Cycles

Dynamic Counter - Enable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.31:

 

http://homepage.ntlworld.com/tbroom/T1.JPG

 

 

3dMark2003 + Everest 2.20 + Super PI 1.4:

 

http://homepage.ntlworld.com/tbroom/T2.JPG

 

 

3dMark2005:

 

T3.JPG

 

 

Aquamark 3d:

 

T4.JPG

 

 

==========

 

 

 

short description:

270x10 @ 2700Mhz, 1.500v + 110%

3-3-8-3 @ 2.7v vdimm

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DFI LANPARTY nF4 SLI-DR - 7/04-2BTA BigToe BIOS

 

AMD Sempron socket939 3200+ (1800Mhz, 256k L2)

 

2x1024MB OCZ PC4000EB (OCZ5002048EBPE-K)

 

Sapphire Radeon X800GTO2 (modded to X850XTPE), 540/590, CAT 5.10 drivers

 

160GB Maxtor IDE

 

NEC 3540A Black IDE DVD-RW Drive

 

Seasonic S12-600 (revA2) ATX 600W Power Supply - Retail

 

 

 

*

*

 

bios_250x9_4000EB-1.gif

 

bios_250x9_4000EB-2.gif

 

bios_250x9_4000EB-3.gif

 

*

*

 

==========

 

[b]Genie BIOS Settings:[/b]

[color=red]

FSB Bus Frequency.............................  -  250

LDT/FSB Frequency Ratio.......................  -  x 3.0

CPU/FSB Frequency Ratio.......................  -  Auto

PCI eXpress Frequency.........................  -  100Mhz



CPU VID StartUp Value.........................  -  1.500v



CPU VID Control...............................  -  1.400v

CPU VID Special Control.......................  -  Above VID * 110%

LDT Voltage Control...........................  -  1.30v 

Chip Set Voltage Control......................  -  1.60v

DRAM Voltage Control..........................  -  2.80v[/color]



[b]DRAM Configuration Settings:[/b]

[color=red]

DRAM Frequency Set............................  -  200=RAM/FSB:01/01

Command Per Clock (CPC).......................  -  Enable [url=http://www.dfi-street.com/forum/showthread.php?p=283613#post283613]EXPLANATION[/url]

CAS Latency Control (Tcl).....................  -  Auto

RAS# to CAS# delay (Trcd).....................  -  Auto

Min RAS# active time (Tras)...................  -  Auto

Row precharge time (Trp)......................  -  Auto

Row Cycle time (Trc)..........................  -  12 Bus Clocks

Row refresh cyc time (Trfc)...................  -  24 Bus Clocks

Row to Row delay (Trrd).......................  -  03 Bus Clocks

Write recovery time (Twr).....................  -  03 Bus Clocks

Write to Read delay (Twtr)....................  -  02 Bus Clocks

Read to Write delay (Trwt)....................  -  03 Bus Clocks

Refresh Period (Tref).........................  -  3120 Cycles

DRAM Bank Interleave..........................  -  Enabled



DQS Skew Control..............................  -  Auto

DQS Skew Value................................  -  0

DRAM Drive Strength...........................  -  Auto

DRAM Data Drive Strength......................  -  Auto

Max Async Latency.............................  -  Auto

DRAM Response Time............................  -  Normal

Read Preamble Time............................  -  Auto

IdleCycle Limit...............................  -  256 Cycles

Dynamic Counter...............................  -  Disable

R/W Queue Bypass..............................  -  16 x

Bypass Max....................................  -  04 x

32 Byte Granularity...........................  -  Disable(4 Bursts)

[/color]

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

http://www.angrygames.com/ocdb/angry/nf4/I...x9_4000EB-1.gif

 

 

3dMark2003:

 

250x9_4000EB-2.gif

 

 

3dMark2005:

 

250x9_4000EB-3.gif

 

 

Aquamark 3d:

 

250x9_4000EB-4.gif

 

 

==========

 

 

 

short description:

250x9 @ 2250Mhz, 1.400v + 110%

3.0-3-7-2 @ 2.8v vdimm

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DFI LANPARTY nF4 "Expert" SLI-DR - 11/11/2005 BIOS

 

AMD Athlon64 4000+ San Diego 1MB L2

 

2x512MB OCZ PC3200 Gold (OCZ4001024ELDCGE-K)

 

XFX GeForce 7800GT, 502/1152 81.85 drivers

 

2x Western Digital "Raptor" 36GB 10,000RPM SATA hdd (RAID-0)

 

NEC 3540A Black IDE DVD-RW Drive

 

Skyhawk 520w 24-pin ATX power supply

 

 

 

*

*

 

bios_nf4xpert_bh5_240x12-1.gif

 

bios_nf4xpert_bh5_240x12-2.gif

 

bios_nf4xpert_bh5_240x12-3.gif

 

*

*

 

==========

 

[b]Genie BIOS Settings:[/b]

[color=red]

FSB Bus Frequency.............................  -  240

LDT/FSB Frequency Ratio.......................  -  Auto

CPU/FSB Frequency Ratio.......................  -  x 12.0

PCI eXpress Frequency.........................  -  100Mhz



CPU VID StartUp Value.........................  -  1.500v



CPU VID Control...............................  -  1.450v

CPU VID Special Control.......................  -  Above VID * 112.0%

LDT Voltage Control...........................  -  1.20v 

Chip Set Voltage Control......................  -  1.52v

DRAM Voltage Control..........................  -  3.52v[/color]



[b]DRAM Configuration Settings:[/b]

[color=red]

DRAM Frequency Set............................  -  200=RAM/FSB:01/01

Command Per Clock (CPC).......................  -  Enable 

CAS Latency Control (Tcl).....................  -  2.0

RAS# to CAS# delay (Trcd).....................  -  02 Bus Clocks

Min RAS# active time (Tras)...................  -  05 Bus Clocks

Row precharge time (Trp)......................  -  02 Bus Clocks

Row Cycle time (Trc)..........................  -  07 Bus Clocks

Row refresh cyc time (Trfc)...................  -  17 Bus Clocks

Row to Row delay (Trrd).......................  -  03 Bus Clocks

Write recovery time (Twr).....................  -  03 Bus Clocks

Write to Read delay (Twtr)....................  -  02 Bus Clocks

Read to Write delay (Trwt)....................  -  03 Bus Clocks

Refresh Period (Tref).........................  -  3120 Cycles

DRAM Bank Interleave..........................  -  Enabled



DQS Skew Control..............................  -  Auto

DQS Skew Value................................  -  0

DRAM Drive Strength...........................  -  Level 05

DRAM Data Drive Strength......................  -  Level 1(Reduce 50%)

Max Async Latency.............................  -  8.0 Nano Seconds

DRAM Response Time............................  -  Normal

Read Preamble Time............................  -  6.0 Nano Seconds

IdleCycle Limit...............................  -  256 Cycles

Dynamic Counter...............................  -  Disable

R/W Queue Bypass..............................  -  16 x

Bypass Max....................................  -  07 x

32 Byte Granularity...........................  -  Disable(4 Bursts)

[/color]

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

http://www.angrygames.com/ocdb/angry/nf4/e...h5_240x12-1.gif

 

 

3dMark2003:

 

nf4xpert_bh5_240x12-2.gif

 

 

3dMark2005:

 

nf4xpert_bh5_240x12-3.gif

 

 

Aquamark 3d:

 

nf4xpert_bh5_240x12-4.gif

 

 

==========

 

 

 

short description:

240x12 @ 2880Mhz, 1.450v + 112.0%

2.0-2-5-5 @ 3.52v vdimm

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DFI LANPARTY nF4 Ultra-D - 6/23-2 Official BIOS

 

AMD Athlon64 3200+ Venice

 

2x512MB G.Skill (F1-3200BWU2) DDR

 

Leadtek PX7800GT 256MB, 480/1150 81.87 drivers

 

WD JD8M 80Gb hdd (8MB cache)

 

Sony DVD RW DRU-710A Optical drive

 

CoolerMaster Real Power 550W

 

 

 

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 250

LDT/FSB Frequency Ratio - X 3.0

CPU/FSB Frequency Ratio - X 10.0

PCI eXpress Frequency - 103Mhz

 

CPU VID StartUp Value - 1.500v

 

CPU VID Control - 1.500v

CPU VID Special Control - Above VID * 110%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.70v

DRAM Voltage Control - 3.30v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200=DRAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.0

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 05 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 08 Bus Clocks

Row refresh cyc time (Trfc) - 12 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 02 Bus Clocks

Refresh Period (Tref) - Auto

Write CAS Latency (Twcl) - 01 Bus Clocks

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase Skew

DQS Skew Value - 0

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 3

Max Async Latency - 7.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 5.0 Nano Seconds

IdleCycle Limit - 032 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Auto

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

prime95.jpg

 

 

3dMark2003:

 

3DMark03.jpg

 

 

3dMark2005:

 

3DMark05.jpg

 

 

Aquamark 3d:

 

Aquamark.jpg

 

 

 

 

==========

 

 

 

short description:

250x10 @ 2500Mhz, 1.500v + 110%

2-2-5-2 @ 3.3v vdimm

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DFI LANPARTY nF4 SLI -D - 7/04-2 BigToe BIOS

 

AMD Athlon64 3000+ Venice

 

OCZ4001024ELDCGE-K

 

BFG 7800 GT OC, 540/1251 +45 DELTA 8.1.8.7 drivers

 

2X80 gig Seagate 7200(8MB cache) Raid Stripe0

 

Sony DRU-710A Dual Layer DVD

 

OCZ PowerStream OCZ600ADJ ATX 600W Power Supply - Retail

 

 

*

*

==========

 

 

Genie BIOS Settings:

FSB Bus Frequency - 310

LDT/FSB Frequency Ratio - AUTO

CPU/FSB Frequency Ratio - 9

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.500v

 

CPU VID Control - 1.525v

CPU VID Special Control - Above VID * 113%

LDT Voltage Control - 1.40v

Chip Set Voltage Control - 1.8v

DRAM Voltage Control - 3.50v

 

DRAM Configuration Settings:

DRAM Frequency Set - 166=RAM/FSB:

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 05 Bus Clocks

Row precharge time (Trp) - 02 Bus Clocks

Row Cycle time (Trc) - 08 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 03 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 02 Bus Clocks

Refresh Period (Tref) - 2560 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level normal 4

DRAM Data Drive Strength - Level 2

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 7.0 Nano Seconds

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.29 + Everest 2.01:

 

 

sp32200511181657010vj.th.gif

 

3dMark2003:

 

 

sp32200511180729588jy.th.gif

 

3dMark2005:

 

sp32200511191352081pz.th.gif

 

 

Aquamark 3d:

 

sp32200511180503178kz.th.gif

 

Everest

 

 

 

sp32200511191624142in.th.gif

 

 

 

==========

 

 

 

short description:

310x9 @ 2792Mhz, 1.525v + 113%

2-2-2-5 @ 3.5v vdimm

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