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Pixel Pipelines


gokusgrill
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As far as I know, pipes handle various specific functions (at least some do). For example, p1a1 may handle calculations only with double float precision, p2a1 may handle geometric calculations, and so on. I believe that you can get a list of what each pipe does from either nVidia or ATI, usually in the form of a... what's the word... programming manual.

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However, I'm not all that sure. Video cards are amazingly complex. What makes it worse is that unless you have really really REALLY steady hands and an electron microscope, you won't be seeing how they truly work deep down for quite awhile. The closest you'll get is a programming optimization PDF (Thank you so much nVidia).

 

And, after reading the stuff at Anandtech, it seems that at least on the X1800XT, each pixel shader quad has a certain job. One handles fog and smoke, the other textures maybe, another Z axis, etc. Distribution like this helps keep bottlenecks down. Each pipeline can do 6 instructions per clock cycle. So, at 500 Mhz, that's... 3,500 4x4 pixel shader blocks, however it also depends on the programmer and optimizations for that specific core.

 

The whole ring bus memory system I'm still trying to grasp, and I sort of just skimmed through that part. Overall, you've gotta respect the guys who build this stuff. It's complex, and while some algorithms are built into the hardware, it has to handle a . load of crap. Not to mention complications regarding the chance of a RAMDAC bottleneck.

Edited by Kamikaze_Badger

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