Today AMD is holding its Next Horizon event, where it has revealed details of some of the upcoming parts the company will be producing for the datacenter, including the Zen 2-based Rome CPU. We can expect Zen 2 to come to consumer parts as well, after the EPYC processors, so some of the information shared here may still be relevant. Some of the information we already know, such as the move to TSMC's 7 nm FinFET process enabling greater density, performance, and efficiency. One aspect of the Zen2 design has only been rumored though, but now it has been confirmed: Zen 2-based Epyc processors will use a separate I/O die.
One of the strengths across all of the Zen and Zen+ processors from AMD has been their use of Infinity Fabric, allowing a single die to be connected with others for different products. While the Ryzen 3/5/7 products use a single die, Threadripper and EPYC CPUs can use two or four, but because these are the same dies used throughout the product stack, these final products are less expensive to make than larger, monolithic design. A disadvantage has been the occasionally higher latency, if one die needs to reach through another to access RAM, and this is especially present on the Threadripper 2970WX and 2990WX where two dies have no direct memory access as well. To address this Zen 2 will use CPU chiplets that house the actual computational cores, and these then connect to a single I/O die, which would handle the connection to the RAM and other devices.
In the slide revealing this design, we also see that while the chiplets will be made on a 7 nm process, the I/O die will actually be on a 14 nm process. Believe it or not, this can actually be another advantage of this design, as some components, like memory controllers, do not necessarily scale down well. Also the 14 nm process may be cheaper to produce, helping to keep costs in check without compromising performance.
Of course it is entirely possible this design characteristic will not come to the Ryzen 3/5/7 products, but it might be employed on Threadripper, which is currently a step between the normal consumer products and server-targeting EPYC chips.
Also shown off at the event was Radeon Instinct MI60, the first 7 nm GPU based on the Vega20 architecture. This will use 32 GB of HBM2 memory and offer 1 TB/s memory bandwidth. With PCIe 4.0 capability it is capable of a 64 GB/s bidirectional connection to the CPU and with Infinity Fabric Links it has 100 GB/s per-link bandwidth between GPUs. It can reach up to 7.4 TFLOPS at FP64, 14.7 at FP32, and 118 TOPS for INT4. The Radeon Instinct MI60 accelerator should be shipping to datacenter customers by the end of the year, and AMD's ROCm open software platform for compute will be available by the end of the year as well.
Back to original news post