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LP JR P45-T2R, E8600, 500x8, 2x2GB Memory 1000MHz, Post 1 of 3

 

DFI LP JR P45-T2R, 10/07 BIOS

500x8, Memory 1000MHz

E8600

2x2GB G.Skill F2-8000CL5-2GBPQ 1000MHz 5-5-5-15

SAPPHIRE 4870

OCZ Core SSD

Orange Slots Used For Memory

 

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main_s.jpg volt_s.jpg

 

click for larger image

dram1_s.jpg dram2_s.jpg

 

click for larger image

clock1_s.jpg clock2_s.jpg

 

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phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM(EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................500 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude....................... 800mV
CPU Clock0 Skew........................... 100ps
CPU Clock0 Skew...........................   0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Special Add.......................Auto
DRAM Voltage Control......................1.908V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.3075
CPU VTT Voltage...........................1.10V
VCore Droop Control.......................Disabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.61X
FSB Vref..................................  2A

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below

Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................5
REF to ACT Delay (tRFC)...................48
Performance Level.........................9
Read Delay Phase Adjust...................Listed Below
MCH ODT Latency...........................Auto
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................5

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DLL and RCOMP Settings   .................Auto
Ch1 DRAM Default Skew.....................Model 3
Ch2 DRAM Default Skew.....................Model 3
RCOMP Setting.............................Model 1

Fine Delay Step Degree....................70ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 2396ps
DIMM 2 Clock fine delay...................Current 2396ps
Ch 1 Control0 fine delay..................Current  268ps
Ch 1 Control1 fine delay..................Current  268ps
Ch 1 Control2 fine delay..................Current  268ps
Ch 1 Control3 fine delay..................Current  268ps
Ch 1 Command fine delay...................Current  394ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 2066ps
DIMM 4 Clock fine delay...................Current 2066ps
Ch 2 Control0 fine delay..................Current   48ps
Ch 2 Control1 fine delay..................Current   48ps
Ch 2 Control2 fine delay..................Current   48ps
Ch 2 Control3 fine delay..................Current   48ps
Ch 2 Command fine delay...................Current  393ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

click for larger image

1000g_lin_64_s.jpg

 

LP JR P45-T2R, E8600, 500x8, 2x2GB Memory 1000MHz, Post 2 of 3

 

XP SP3

 

 

click for larger image

1000g_occt_xp_s.jpg

 

 

click for larger image

1000g_3d06_xp_s.jpg

 

 

1000g_crysis_xp.jpg1000g_ut3_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 14min 05sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1000g_everest_xp_s.jpg

 

LP JR P45-T2R, E8600, 500x8, 2x2GB Memory 1000MHz, Post 3 of 3

 

Vista 64 Bit SP1

 

 

click for larger image

1000g_occt_64_s.jpg

 

 

click for larger image

1000g_3d06_64_s.jpg

 

 

click for larger image

1000g_3dvan_64_s.jpg

 

 

click for larger image

1000g_pcvan_64_s.jpg

 

 

1000g_crysis_64.jpg1000g_ut3_64.jpg

 

 

3dx Max w/V-ray

Time to render: 15min 15sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

click for larger image

1000g_everest_64_s.jpg

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LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 1 of 3

 

DFI LP JR P45-T2R, 10/30 BIOS

550x8, Memory 1100MHz

E8600

2x2GB OCZ PC2-9200 Flex II 1050MHz 5-5-5-18

SAPPHIRE 4870

OCZ Core SSD

Orange Slots Used For Memory

 

click for larger image

main_s.jpg volt_s.jpg

 

click for larger image

dram1_s.jpg dram2_s.jpg

 

click for larger image

clock1_s.jpg clock2_s.jpg

 

click for larger image

phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM(EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 8x
CPU N/2 Ratio.............................Disabled
CPU Clock.................................550 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude....................... 800mV
CPU Clock0 Skew........................... 200ps
CPU Clock0 Skew...........................   0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Special Add.......................+175.0mV
DRAM Voltage Control......................1.957V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.3575
CPU VTT Voltage...........................1.18V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.61X
FSB Vref..................................  2A

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below

Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................5
Precharge Delay (tRAS)....................15
All Precharge to Act......................5
REF to ACT Delay (tRFC)...................54
Performance Level.........................10
Read Delay Phase Adjust...................Listed Below
Write to PRE Delay (tWR)..................13
Rank Write to Read (tWTR).................10
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................5

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DLL and RCOMP Settings   .................By Menu
Ch1 DRAM Default Skew.....................Model 5
Ch2 DRAM Default Skew.....................Model 5
RCOMP Setting.............................Model 0

Fine Delay Step Degree....................70ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 2476ps
DIMM 2 Clock fine delay...................Current 2476ps
Ch 1 Control0 fine delay..................Current  472ps
Ch 1 Control1 fine delay..................Current  472ps
Ch 1 Control2 fine delay..................Current  410ps
Ch 1 Control3 fine delay..................Current  394ps
Ch 1 Command fine delay...................Current  472ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 2492ps
DIMM 4 Clock fine delay...................Current 2428ps
Ch 2 Control0 fine delay..................Current  442ps
Ch 2 Control1 fine delay..................Current  442ps
Ch 2 Control2 fine delay..................Current  346ps
Ch 2 Control3 fine delay..................Current  332ps
Ch 2 Command fine delay...................Current  442ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

click for larger image

1100f_lin_64_s.jpg

 

LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 2 of 3

 

XP SP3

 

 

click for larger image

1100f_occt_xp_s.jpg

 

 

click for larger image

1100f_3d06_xp_s.jpg

 

 

1100f_crysis_xp.jpg1100f_ut3_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 14min 05sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

TMPGEnc XPress

1GB VOB file ripped from DVD movie

 

click for larger image

1100f_encode_xp_s.jpg

 

 

click for larger image

1100f_everest_xp_s.jpg

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LP JR P45-T2R, E8600, 550x8, 2x2GB Memory 1100MHz, Post 3 of 3

 

Vista 64 Bit SP1

 

 

click for larger image

1100f_occt_64_s.jpg

 

 

click for larger image

1100f_3d06_64_s.jpg

 

 

click for larger image

1100f_3dvan_64_s.jpg

 

 

click for larger image

1100f_pcvan_64_s.jpg

 

 

1100f_crysis_64.jpg1100f_ut3_64.jpg

 

 

3dx Max w/V-ray

Time to render: 15min 15sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

TMPGEnc XPress

1GB VOB file ripped from DVD movie

 

click for larger image

1100f_encode_64_s.jpg

 

 

click for larger image

1100f_everest_64_s.jpg

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Nice going man, can't remember the last time I've seen such results from you since the Infinity, or perhaps I've been under a rock somewhere? :lol:

 

In any case, between your results and Kitfit's, I definitely need an E8600.

 

Like, now. :thumbs-up:

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Thanks guys. This board has tured out to be a lot of fun.

 

Now that is the kind of mATX board the overclocker world was waiting for! :)

One can't really ask for more out of this type of board. Used as intended, 500x8 seems to be the sweet spot. Can run 24/7 at default voltages. For 24/7 use the board might have a bit more left in it. Hopefully will have some screenshots posted up in the next few days.

 

nice work Praz... nice to see DFI's growing army of motherboards again :)

DFI has really stepped up to the plate with the last few boards that have been released. Hopefully it continues. Guess I'll find out real soon.

 

Nice going man, can't remember the last time I've seen such results from you since the Infinity, or perhaps I've been under a rock somewhere? :lol:

 

In any case, between your results and Kitfit's, I definitely need an E8600.

 

Like, now. :thumbs-up:

More of my time is spent behind the scene now. I do try to post a few screenshots once in a while though.

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LP JR P45-T2R, E8600, 575x7.5, 2x2GB Memory 1152MHz, Post 1 of 3

 

DFI LP JR P45-T2R, 10/30 BIOS

575x7.5, Memory 1152MHz

E8600

2x2GB OCZ PC2-9200 Flex II 1050MHz 5-5-5-18

SAPPHIRE 4870

OCZ Core SSD

Orange Slots Used For Memory

 

click for larger image

main_s.jpg volt_s.jpg

 

click for larger image

dram1_s.jpg dram2_s.jpg

 

click for larger image

clock1_s.jpg clock2_s.jpg

 

click for larger image

phase_s.jpg feature_s.jpg

 

 

[color="Red"]CPU Feature Page[/color]
Thermal Management Control................Enabled
PPM(EIST) Mode............................Enabled
Limit CPUID MaxVal........................Disabled
CIE Function..............................Auto
Execute Disable Bit.......................Enabled
Virtualization Technology.................Enabled
Core Multi-Processing.....................Enabled

[color="Red"]Main BIOS Page[/color]
Exist Setup Shutdown......................Mode 2
Shutdown after AC loss....................Enabled
AC Shutdown free..........................Enabled
O.C. Fail Retry Counter...................1
O.C. Fail CMOS Reload.....................Disabled
CPU Clock Ratio........................... 7.5x
CPU N/2 Ratio.............................Enabled
CPU Clock.................................575 MHz
Boot Up Clock.............................Auto
CPU Clock Amplitude....................... 800mV
CPU Clock0 Skew........................... 200ps
CPU Clock0 Skew...........................   0ps
DRAM Speed................................333/667
PCIE Clock................................100MHz

CPU Spread Spectrum.......................Disabled
PCIE Spread Spectrum......................Disabled

[color="Red"]Voltage Setting Page[/color] 
CPU VID Special Add.......................+137.5mV
DRAM Voltage Control......................2.001V
SB Core/CPU PLL Voltage...................1.55V
NB Core Voltage...........................1.4075
CPU VTT Voltage...........................1.26V
VCore Droop Control.......................Enabled
Clockgen Voltage Control..................3.45V
CPU GTL 0/2 REF Volt......................0.67X
CPU GTL 1/3 REF Volt......................0.67X
North Bridge GTL REF Volt ................0.61X
FSB Vref..................................  2A

[color="Red"]DRAM Timing Page[/color]
Enhance Data Transmitting.................Fast
Enhance Addressing........................Fast
T2 Dispatch...............................Auto
Clock Setting Fine Delay..................Listed Below

Flex Memory Mode..........................Auto
CAS Latency Time (tCL)....................5
RAS# to CAS# Delay (tRCD).................5
RAS# Precharge (tRP)......................Auto
Precharge Delay (tRAS)....................15
All Precharge to Act......................8
REF to ACT Delay (tRFC)...................60
Performance Level.........................10
Read Delay Phase Adjust...................Listed Below
Write to PRE Delay (tWR)..................14
Rank Write to Read (tWTR).................11
ACT to ACT Delay (tRRD)...................3
Read to Write Delay (tRDWR)...............8
Ranks Write to Write (tWRWR)..............Auto
Ranks Write to Read (tWRRD)...............Auto
Read CAS# Precharge (tRTP)................3
ALL PRE to Refresh........................8

[color="Red"]Read Delay Phase Adjust Page[/color]
Channel 1 Phase 0 Pull-In.................Auto
Channel 1 Phase 1 Pull-In.................Auto
Channel 1 Phase 2 Pull-In.................Auto
Channel 1 Phase 3 Pull-In.................Auto
Channel 1 Phase 4 Pull-In.................Auto

Channel 2 Phase 0 Pull-In.................Auto
Channel 2 Phase 1 Pull-In.................Auto
Channel 2 Phase 2 Pull-In.................Auto
Channel 2 Phase 3 Pull-In.................Auto
Channel 2 Phase 4 Pull-In.................Auto

[color="Red"]Clock Setting Fine Delay Page[/color]
DLL and RCOMP Settings   .................By Menu
Ch1 DRAM Default Skew.....................Model 5
Ch2 DRAM Default Skew.....................Model 5
RCOMP Setting.............................Model 0

Fine Delay Step Degree....................70ps


Ch1 Clock Crossing Setting................Auto
DIMM 1 Clock fine delay...................Current 2476ps
DIMM 2 Clock fine delay...................Current 2476ps
Ch 1 Control0 fine delay..................Current  472ps
Ch 1 Control1 fine delay..................Current  472ps
Ch 1 Control2 fine delay..................Current  410ps
Ch 1 Control3 fine delay..................Current  394ps
Ch 1 Command fine delay...................Current  472ps

Ch2 Clock Crossing Setting................Auto
DIMM 3 Clock fine delay...................Current 2492ps
DIMM 4 Clock fine delay...................Current 2428ps
Ch 2 Control0 fine delay..................Current  442ps
Ch 2 Control1 fine delay..................Current  442ps
Ch 2 Control2 fine delay..................Current  346ps
Ch 2 Control3 fine delay..................Current  332ps
Ch 2 Command fine delay...................Current  442ps

Ch1Ch2 CommonClock Setting................Auto

Ch1 RDCAS GNT-Chip Delay..................Auto
Ch1 WRCAS GNT-Chip Delay..................Auto
Ch1 Command to CS Delay...................Auto

Ch2 RDCAS GNT-Chip Delay..................Auto
Ch2 WRCAS GNT-Chip Delay..................Auto
Ch2 Command to CS Delay...................Auto

 

 

click for larger image

1150f_lin_64_s.jpg

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LP JR P45-T2R, E8600, 575x7.5, 2x2GB Memory 1152MHz, Post 2 of 3

 

XP SP3

 

 

click for larger image

1150f_occt_xp_s.jpg

 

 

click for larger image

1150f_3d06_xp_s.jpg

 

 

1150f_warhead_xp.jpg1150f_farcry2_xp.jpg

 

 

3dx Max w/V-ray

Time to render: 13min 05sec

 

click for larger image

lounge_night_benchmark_680.jpg

 

 

TMPGEnc XPress

1GB VOB file ripped from DVD movie

 

click for larger image

1150f_encode_xp_s.jpg

 

 

click for larger image

1150f_cin_xp_s.jpg

 

 

click for larger image

1150f_everest_xp_s.jpg

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