166 Divider Has a Limit?

[Capt Proton]

This problem also applies to my OCZ PC4000 Plat XTC 2 Gbs as well.

Rig is stable (Prime 95, 3D Mark 03, OCCT etc) with CPU at 300 X 10 and memory at 250MHz with the 166 Divider. If I raise the HTT to 310, it freezes just before the Check Sum (Edit:Verifying DMI not Check Sum) message during the boot process and POSTS again. Now, if I put HTT to 260MHz, and set the memory to 200 (1:1), it boots with no problem. I won't say its stable, as I have not tried to do a complete set of tests with this config. My OCZ definitely was not stable.

If I set the HTT to 310MHz and my divider to 180, it will boot up no problem with my Centon TCCD. I didn't try using the OCZ, as I didn't think it had a prayer of running that fast. The Centon isn't stable yet at 281MHz, but it will boot and run.

Any ideas as to why it won't boot using the 166 divider at 310MHz?

Here's the settings I'm using that are Stable with my Centon. OCZ settings were different.

 

FSB Bus Frequency............................. 300

LDT/FSB Frequency Ratio....................... X3

CPU/FSB Frequency Ratio....................... 10

PCI eXpress Frequency......................... 100

 

CPU Voltage .................................. 1.400v * 113%

LDT Voltage .................................. 1.40v

ChipSet (NF4) Voltage ........................ 1.70V

DRAM Voltage ................................. 2.8V

+0.03 if not 3.2V ............................ Disabled (tried Enabled too)

 

Memclock (DRAM Frequency) .................... 166

1T/2T Timing (Command Per Clock).............. 1T

CAS Latency (Tcl)............................. 2.5

RAS# to CAS# delay (Trcd)..................... 3

Min RAS# active time (Tras)................... 5

Row precharge time (Trp)...................... 3

Row Cycle time (Trc).......................... 7

Row refresh cyc time (Trfc)................... 14

Row to Row delay (Trrd)....................... 2

Write recovery time (Twr)..................... 2

Write to Read delay (Twtr).................... 2

Read to Write delay (Trwt).................... 3

Refresh Period (Tref)......................... 3072

DRAM Bank Interleave.......................... Enabled

 

DQS Skew Control.............................. Inc

DQS Skew Value................................ 255

DRAM Drive Strength........................... Weak 4

DRAM Data Drive Strength...................... Level 2

Max Async Latency............................. 8ns

DRAM Response Time............................ Normal

Read Preamble Time............................ 5ns

IdleCycle Limit............................... 32

Dynamic Counter............................... Enable

R/W Queue Bypass.............................. 8x

Bypass Max.................................... 7x

32 Byte Granularity........................... Disable

[Zelig]

Try disabling CPC, I've been playing around with some new (to me) ram and cpu, and can't get any of the dividers to work with CPC enabled.