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gearhead364

Stability problems . . .

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I need some suggestions on stabilizing my rig; I have been using he DFI Overclocking Guide. So far I have found my max CPU speed to be 2970 MHz (330 x 9) with 1.40v; I have also found my maximum ram speed to be 255 MHz at 3-4-3-8. My proble seems to be the dividers, I have been using the 150 MHz (03/04) so that my CPU will run at 2970 and my ram will run at 247 MHz. With these settings I am able to boot in to windows, but Prime fails with in 1 min. My ram is Samsung UCCC and I have some really loose timings right now. Any suggestions on how to stabilize my system?

 

vDIMM - 2.5v

DRAM Frequency Set - 3:4

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3

RAS# to CAS# delay (Trcd) - 4 Bus Clocks

Min RAS# active time (Tras) - 8 Bus Clocks

Row precharge time (Trp) - 4 Bus Clocks

Row Cycle time (Trc) - 17 Bus Clocks

Row refresh cyc time (Trfc) - 24 Bus Clocks

Row to Row delay (Trrd) - 4 Bus Clocks

Write recovery time (Twr) - 3 Bus Clocks

Write to Read delay (Twtr) - 2 Bus Clocks

Read to Write delay (Trwt) - 4 Bus Clocks

Refresh Period (Tref) - 2560

DRAM Bank Interleave - Enabled

 

DQS Skew Control - off

DQS Skew Value - 0

DRAM Drive Strength - 6

DRAM Data Drive Strength - 1

Max Async Latency - 08.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 06.5 Nano Seconds

IdleCycle Limit - 256 Cycles

Dynamic Counter - Enable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

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Guest caffeinejunkie

Hmm try this with those settings:

 

DRAM Frequency Set - 150=RAM/FSB:3/4

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3.0

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 12 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3684 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 7

DRAM Data Drive Strength - Level 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 6.0 Nano Seconds

IdleCycle Limit - 016 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

 

and w/ 2.6v

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Hmm try this with those settings:

 

DRAM Frequency Set - 150=RAM/FSB:3/4

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3.0

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 12 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3684 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 7

DRAM Data Drive Strength - Level 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 6.0 Nano Seconds

IdleCycle Limit - 016 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

 

and w/ 2.6v

 

 

I will try those in a few minutes, but should I set the Tref for 3684, I thought that was for 100 MHz.

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