Serious Stability Issues

[SBB]

I have a serious stability problem with my system

 

With everything stock, I run super-pi and it fails on one of the two cores instantly. Seems to be switching between which one aswell :/

 

Please advise!

[lowboy]

More information would be helpful, new build,following the build guide. For memory try these settings:

DRAM Frequency Set - 200=RAM/FSB:1/1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 06 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 09 Bus Clocks

Row refresh cyc time (Trfc) - 12 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 01 Bus Clocks

Read to Write delay (Trwt) - 02 Bus Clocks

Refresh Period (Tref) - 2064 Cycles

Write CAS Latency (Twcl) - 01

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Auto

DRAM Data Drive Strength - auto

Max Async Latency - Auito

DRAM Response Time - normal

Read Preamble Time - Auto

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

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[Guest Kobalt]

I advise you to run memtest86, and if that passes, move on to prime95. That should take about 3-4 hours testing in each program. (at least)

[SBB]

Lowboy's settings still produce errors!

 

I will run memtest and see what happens

[SBB]

Anything other than dead RAM be causing problems with Memtest?

[SBB]

Tried with the RAM at 2.8v, as suggested on crucial site, still a load of errors in Memtest

[smolt]

what test are you getting errors in?

[Guest caffeinejunkie]

give this a go:

 

DRAM Frequency Set - 200=RAM/FSB:1/1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2.5

RAS# to CAS# delay (Trcd) - 02 Bus Clocks

Min RAS# active time (Tras) - 06 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 12 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - 01

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - 7

DRAM Data Drive Strength - 3

Max Async Latency - 9

DRAM Response Time - normal

Read Preamble Time - 6.5

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

[Guest Kobalt]

Tried with the RAM at 2.8v, as suggested on crucial site, still a load of errors in Memtest

At least you found your problem.

 

To fix it try different timings. You may even have to try vastly slower ones.

 

If that don't work, then RMA the RAM.

[SBB]

Tested in another board, RAM is mashed.

 

Will get a new kit asap