_man1c_ Posted June 17, 2006 Posted June 17, 2006 yea 3rs. min. thats where i had my first error. Share this post Link to post Share on other sites More sharing options...
RubberNeck Posted June 18, 2006 Posted June 18, 2006 4 hrs memtest stable and xp installed!! Thanks guys Share this post Link to post Share on other sites More sharing options...
red930 Posted June 18, 2006 Posted June 18, 2006 Resolved Share this post Link to post Share on other sites More sharing options...
_man1c_ Posted June 18, 2006 Posted June 18, 2006 4 hrs memtest stable and xp installed!! Thanks guys mine is bout to do the same thing . gonna let it run all through the 8hrs though. using the exact same timings this is great. now ill have my own computer again. YAY!! Share this post Link to post Share on other sites More sharing options...
wevsspot Posted June 18, 2006 Posted June 18, 2006 The HZ's have a little more to give. Try these timings and see what happens. Here are my final settings and results. Anything above 270FSB was a no go at 1:1, so I settled in at 260X11 and 1:1, fairly tight timings and performance is great. Was hoping for that 275FSB 1:1 nirvana, but just wasn't going to happen. I'm happy at this point as I was able to squezze some more out of my Sandy. Genie BIOS Settings: FSB Bus Frequency - 260 LDT/FSB Frequency Ratio - 3 CPU/FSB Frequency Ratio - 11 PCI eXpress Frequency - 100Mhz CPU VID StartUp Value - 1.425v CPU VID Control - 1.375v CPU VID Special Control - Above VID * 113% LDT Voltage Control - 1.30v Chip Set Voltage Control - 1.70v DRAM Voltage Control - 2.66v DRAM Configuration Settings: DRAM Frequency Set - 200 = RAM/FSB 1:1 Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 03 RAS# to CAS# delay (Trcd) - 04 Bus Clocks Min RAS# active time (Tras) - 08 Bus Clocks Row precharge time (Trp) - 03 Bus Clocks Row Cycle time (Trc) - 07 Bus Clocks Row refresh cyc time (Trfc) - 14 Bus Clocks Row to Row delay (Trrd) - 02 Bus Clocks Write recovery time (Twr) - 02 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trwt) - 03 Bus Clocks Refresh Period (Tref) - 3684 Cycles Write CAS Latency (Twcl) - 01 DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - 6 DRAM Data Drive Strength - 3 Max Async Latency - 8.0 Nano Seconds DRAM Response Time - Normal Read Preamble Time - 5 Nano Seconds IdleCycle Limit - 16 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(4 Bursts) Share this post Link to post Share on other sites More sharing options...
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