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cant get it out of standby


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I've had my computer for about 7 months now and never really attempted to put it into stanby, anyway i came to try it the other day and everything went ok, until i tried to resume.

 

I've set in windows to use minimal power management, and in the bios i've set ACPI to enabled (as was default) and the type of suspend to S3. (i dnt like using S1 because it leaves the fans running)

 

Anyway when i try to resume, all the fans start to spin at full speed, as they would when i turn my system on for the first 3 seconds, i guess before the bios kicks in, but instead of slowing down they stayed at full speed. I can hear my hard drive come back to life, but theres no sign of life from the keyboard, mouse, or monitor, and the power LED on the front of the case continues to blink. The diagnostic LED's on the motherboard show 3, which in the manual says is a CPU problem. To get this to stop i have to hold the power button down for the 4 secs to hard restart it.

 

I've tried reinstalling the nVidia chipset and graphics drivers but this doesnt help, and i dont really know if anything else in the bios needs to be changed. I've looked through the other forumns on here, and a couple of people have had this on nF3 boards, but came to no resolution.

 

Any advice would be helpful.

 

Thanks in advance, Ben.

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Here is information from AMD site. It may explain why S3 is not working stable on DFI boards.

 

http://www.amd.com/us-en/assets/content_ty..._docs/25759.pdf

 

85 Insufficient Delay Between MEMCLK Startup and CKE Assertion

During Resume From S3

Description

When sequencing the DRAMs out of self refresh during a resume from the S3 (Suspend-to-RAM)

state, the processor fails to insert sufficient delay between MEMCLK startup and CKE assertion.

Potential Effect on System

Memory system failure leading to unpredictable system failure.

Suggested Workaround

Modify the resume from S3 BIOS sequence such that sufficient delay is inserted between the time

MEMCLK is enabled in the DRAM Config High Register (Dev:2x94) and the time the ESR and

SR_S bits are written in the DRAM Config Low Register (Dev:2x90[13:12]) to exit self refresh. For

registered DIMMs, 100 μs of delay is required. For unbuffered DIMMs, 10 μs of delay is required.

Fix Planned

No

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Thanks for the help, but i'm not that confident with computers, and i'm having trouble understanding what this actually means. Also the whole of the "workaround" doesnt really make much sense to me, if anyone can give me some advice or point me in the right direction it'd be really helpful, cheers.

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  • 1 month later...

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