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ooztuncer

G.Skill HZ/Any other UCCC (2x1024) 260+ please post here

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Prime95 Stable 12+ Hours

 

http://img382.imageshack.us/img382/3851/30...e95stableg1.jpg

 

302htt180dividerprime95stableg1.jpg

 

http://img382.imageshack.us/img382/2428/30...me95stableg.jpg

 

302htt180dividerprime95stableg.jpg

 

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Bios Settings

 

http://img147.imageshack.us/img147/8620/bios14ao.jpg

 

bios14ao.jpg

 

http://img147.imageshack.us/img147/7530/bios27tb.jpg

 

bios27tb.jpg

 

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Dram Settings

 

http://img115.imageshack.us/img115/4381/dramconfig15zm.jpg

 

dramconfig15zm.jpg

 

http://img115.imageshack.us/img115/9634/dramconfig28ts.jpg

 

dramconfig28ts.jpg

 

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277Mhz as memtest- and primestable as my SanDiego [email protected],37V. I like my watercooling temps (roomtemp at about 18°C) :D

Watch my low VDimm, the UCCC really clock well with ~2,5V...

 

hm2w2N9K.jpg

 

@Saruman U really should decrease ur "idle cycle limit" to 16 or 32. 256 clks isn´t necessary and gives u a great loose in performance

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Here are my final settings and results. Anything above 270FSB was a no go at 1:1, so I settled in at 260X11 and 1:1, fairly tight timings and performance is great. Was hoping for that 275FSB 1:1 nirvana, but just wasn't going to happen. I'm happy at this point as I was able to squezze some more out of my Sandy.

 

Genie BIOS Settings:

FSB Bus Frequency - 260

LDT/FSB Frequency Ratio - 3

CPU/FSB Frequency Ratio - 11

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.425v

 

CPU VID Control - 1.375v

CPU VID Special Control - Above VID * 113%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.70v

DRAM Voltage Control - 2.66v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3684 Cycles

Write CAS Latency (Twcl) - 01

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - 6

DRAM Data Drive Strength - 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 5 Nano Seconds

IdleCycle Limit - 16 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

==========

 

 

Prime95 + 3dMark2001SE + CPU-Z 1.31 + Everest 2.20:

 

primeeverest3dmark01cpuz260x11.th.jpg

 

 

3dMark2003:

 

3dmark03260x116uo.th.jpg

 

 

3dMark2005:

 

3dmark05superpi260x117dk.th.jpg

 

 

Aquamark 3d:

 

aquamark3260x110wy.th.jpg

 

 

==========

 

 

 

short description:

260x11 @ 2860Mhz, 1.375v + 113%

3.0-4-8-3 @ 2.66v vdimm

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Way to go Wevsspot! Gotta try out your settings..i'll post mine up when I have some extra time....I like the way you achieved your killer OC...hate to admit it but mine was dumb luck...mostly "auto" settings with the cpu vidd bumped up to a corrected 1.47. Havent tried to tighten the timings yet. I was so happy to just get where I am, I'm almost afraid to tempt fate! Good job man!

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Hey, I understand. That's why I've got three different posts over at the OCDB with G.Skill RAM. It was very much trial and error. But thanks to a ton of posts by other G.Skill HZ users here, it gave me a starting point. Like I said, didn't reach the 275 1:1 I had hoped when I purchased, but I'm very happy with where I've got.

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Hey Guys,

I just sold my 2GBHZ kit because my old Mushkin Redlines just got back from RMA but it was pretty good while I had it! I'll post a screenies from my "Overclocking Database entry. This is my Prime95 + 3DMark01SE shot. My kit was very stable up to about 268Mhz but I kept it at 265Mhz at 3-4-4-8 which seemed to be the sweet spot at 1:1.

 

one8vv.th.jpg

 

Genie BIOS Settings:

FSB Bus Frequency - 265

LDT/FSB Frequency Ratio - 3x

CPU/FSB Frequency Ratio - 11.0x

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - Startup

 

CPU VID Control - 1.325v

CPU VID Special Control - Above VID * 112.0%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.62v

DRAM Voltage Control - 2.71v

 

DRAM Configuration Settings:

DRAM Frequency Set - 200=RAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 15 Bus Clocks

Row refresh cyc time (Trfc) - 17 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 04 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - Auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Auto

DRAM Data Drive Strength - Auto

Max Async Latency - 7.0ns

DRAM Response Time - Fastest

Read Preamble Time - 5.5ns

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

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Hey all,

 

Just wanted to say thanks to everyone's contributions so far. I'm on a quest to hit 270 so I can run at 9/10. I had almost given up hope before I found this thread, while nothing specifically helped me seeing that 270 is definantly achievable I renewed my efforts and used some of your postings as starting points. I'm guessing I've put about 10-15 hours into this RAM (not counting testing) with it ALWAYS failing at 98% on the first run of Test #5. Specifically in the last 5-10MB with error-bits 02000000 to the tune of 20-50K errors depending on the settings used.

 

I was starting to get dismayed again after trying almost every sensible range and combination of settings when I applied some "last ditch logic". I was thinking that since it fails in the same point in the second stick of RAM, it must be weaker, so maybe if I swap the two sticks the weaker one can nuzzle up under my giant Zalman and benefit from the unintentional cooling. Low and behold, I started up test #5 and it passed clean through 8 times before getting two errors.

 

Anyways just thought I'd add this tidbit in case it saves anyone else some sanity. I'm not out of the woods yet, but at least I can see some sunlight through the treetops.

 

Now off to start the whole process over for a third time but I'm hopeful once again.

 

Thanks again guys.

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I had to loosen my timings considerably to hit 270 stable with these things... Then I tightened them as much as I could. Check it out... http://www.dfi-street.com/forum/showpost.p...8&postcount=141

 

Hey all,

 

Just wanted to say thanks to everyone's contributions so far. I'm on a quest to hit 270 so I can run at 9/10. I had almost given up hope before I found this thread, while nothing specifically helped me seeing that 270 is definantly achievable I renewed my efforts and used some of your postings as starting points. I'm guessing I've put about 10-15 hours into this RAM (not counting testing) with it ALWAYS failing at 98% on the first run of Test #5. Specifically in the last 5-10MB with error-bits 02000000 to the tune of 20-50K errors depending on the settings used.

 

I was starting to get dismayed again after trying almost every sensible range and combination of settings when I applied some "last ditch logic". I was thinking that since it fails in the same point in the second stick of RAM, it must be weaker, so maybe if I swap the two sticks the weaker one can nuzzle up under my giant Zalman and benefit from the unintentional cooling. Low and behold, I started up test #5 and it passed clean through 8 times before getting two errors.

 

Anyways just thought I'd add this tidbit in case it saves anyone else some sanity. I'm not out of the woods yet, but at least I can see some sunlight through the treetops.

 

Now off to start the whole process over for a third time but I'm hopeful once again.

 

Thanks again guys.

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here is the bios timing for ultra-d

 

FSB 250+; DDR500+

 

DRAM FREQUENCY SET: 200 (1:1)

COMMAND PER CLOCK: ENABLE (1T)

CAS: 3

TRCD: 4

TRAS: 8

TRP: 4

TRC: 7

TRFC: 13~18

TRRD: 2

TER: 2

TWTR: 1~2

TRWT: 2~3

TREF: 3684

TWCL: 1

DRAM BANK INTERLEAVE: ENABLE

 

DQS SKEW CONTROL: AUTO

DQS SKEW VALUE: 0

DRAM DRIVE STRENGTH: 7 (OR BEST VALUE FOR YOUR SYSTEM)

DARM DATE DRIVE STRENGTH: 1 (OR BEST VALUE FOR YOUR SYSTEM)

MAX ASYNC LATENCY: 7~8NS

DARM RESPONSE: NORMAL

READ PREAMBLE TIME: 5NS

IDLECYCLE LIMIT: 256

DYNAMIC COUNTER: ENABLE

R/W QUEUE BYPASS:16

BYPASS MAX: 7

32 BYTE GRANULARITY: DISABLE

 

Any recommandations for a NF3 250Gb (754) board ?? (sadly no G-Skills !!)

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Nice OC d3M0n!

 

Hopefully I can get mine stable at 270, I didn't have time to put it through more than a handful of configurations last night.

 

A quick question. Would it be better to run this RAM with a 09/10 divider at 270 with semi loose settings, or tighter timings with a 05/06 divider at 245.5. I was able to get my memory to run at 2.5-3-3-8 @ 245.5 with everything else at Auto for 45 mins before failing test 5 so with some tweaking it should be able to run stable hopefully.

 

I read through Angry's thread on the subject but he is comparing two diffferent brands of memory so I don't think its a good representation of this situation. What is the general consensus on this memory? 09/10 divider with loser timings, or 05/06 with tighter? Also I'm not concerend with pure benchmark numbers as much as I am true impact on gaming/video/audio encoding etc.

 

I will continue to research and experiement, just trying to decide which path to tackle first and thought someone might have some experience.

 

I had to loosen my timings considerably to hit 270 stable with these things... Then I tightened them as much as I could. Check it out... http://www.dfi-street.com/forum/showpost.p...8&postcount=141

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