Jump to content

G.Skill HZ/Any other UCCC (2x1024) 260+ please post here


ooztuncer

Recommended Posts

  • Replies 556
  • Created
  • Last Reply

Top Posters In This Topic

No it's not pointless. You need to verify that the memory will operate error free with your current settings with Memtest before booting into Windows. Without these results if Memtest for Windows fails you won't know if it's timings Windows doesn't like or faulty memory.

Share this post


Link to post
Share on other sites

Johnny,

 

Use these settings as a starting point;

 

 

Genie BIOS Settings:

 

FSB Bus Frequency - 260

LDT/FSB Frequency Ratio - 3

CPU/FSB Frequency Ratio - 10

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - 1.425v

 

CPU VID Control - 1.375v

CPU VID Special Control - Above VID * 113%

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.70v

DRAM Voltage Control - 2.66v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3684 Cycles

Write CAS Latency (Twcl) - 01

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - 6

DRAM Data Drive Strength - 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 5 Nano Seconds

IdleCycle Limit - 16 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

This is using 07/04-2bta BIOS

Share this post


Link to post
Share on other sites

I've tried booting to windows at 260 but i can only do that at 2.8v. And when i test the ram the pc crashes.

I think i'm going to give up.

 

If the ram works at it's rated speed of 250mhz don't beat your head against the wall...put em' at 2.6v and work on getting the most out of your cpu.

Share this post


Link to post
Share on other sites

If the ram works at it's rated speed of 250mhz don't beat your head against the wall...put em' at 2.6v and work on getting the most out of your cpu.

 

Absolutely, CPU clocks are king! I'd rather be able to run my X2 4800 at 2.75ghz and memory at 500mhz. Which by the way is what I'm doing right now, used a 9/10 divider to get the memory down to a frequency where it would play pretty with my X2.

Share this post


Link to post
Share on other sites

Well ok i think i'll give it up. I was just expecting more since i just had a bad experience with ram. I had one kit of redline xp 4000 then i bought another to have 2g, but one of them went to rma about a month ago and the other just last week. It was the reason why i bought the gskill hz after all.

Share this post


Link to post
Share on other sites

Well, drop your CPU multiplier down, crank up the FSB and try the timings I sent you. They should be good up to around 530mhz (memory controller on your cpu willing).

 

Speaking of which, remember on A64 the on-die memory controller is just as responsible as your RAM for determining how good your clocks go.

Share this post


Link to post
Share on other sites

Ultra-D 0623-3

FSB - 260

LDT - x4

CPU/FSB Ratio - x11

Vcore - 1.39

LDTv - 1.30

CHPv - 1.60

vDIMM - 2.54

 

DRAM Frequency Set - 200=RAM/FSB:01/01

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 3.0

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3072 Cycles

Write CAS Latency (Twcl) - 1

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase

DQS Skew Value - 0

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 5.5 Nano Seconds

IdleCycle Limit - 256 Cycles

Dynamic Counter - Enable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

Share this post


Link to post
Share on other sites

Please sign in to comment

You will be able to leave a comment after signing in



Sign In Now

×
×
  • Create New...