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G.Skill HZ/Any other UCCC (2x1024) 260+ please post here

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try: 250-4-8-100-1.4-1.62-2.84 - 200-enable-3-4-8-4-10-14-2-2-2-3-3120-1-enable-increase-255-7-1-9-normal-6.5-32-disable-16-7-disable

 

ok 15 passes with 54 errors on test5 test 14 had 6 errors so 9 passes with errors and 6 with none.

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ok 15 passes with 54 errors on test5 test 14 had 6 errors so 9 passes with errors and 6 with none.

 

try: 250-4-8-100-1.4-1.62-2.84 - 200-enable-3-4-8-4-10-14-2-2-2-3-3120-1-enable-increase-255-8-4-9-normal-7.0-256-disable-16-7-disable

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I have two sets for you guys

Here is the Tight 260 timings...

If there is any settings to make it tighter let me know

I get 6850 in Everest home.

 

FSB Bus Frequency - 260

LDT/FSB Frequency Ratio - 3

CPU/FSB Frequency Ratio - 9

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - AUTO

 

CPU VID Control - 1.375v

CPU VID Special Control - Auto

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 2.6v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 03 Bus Clocks

Row Cycle time (Trc) - 07 Bus Clocks

Row refresh cyc time (Trfc) - 14 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 4708 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Increase

DQS Skew Value - 255

DRAM Drive Strength - weak4 (level 7)

DRAM Data Drive Strength - 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 6.0 Nano Seconds (this causes errors at 5)

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

8 Hour memtest 5 error free and 8hour dual prime

- I had a 120mm fan over the ram aswell.

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This is the 270 semistable..

If there is any settings to make it more stable let me know

 

FSB Bus Frequency - 270

LDT/FSB Frequency Ratio - 3

CPU/FSB Frequency Ratio - 9

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - AUTO

 

CPU VID Control - 1.375v

CPU VID Special Control - Auto

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 2.6v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 13 Bus Clocks

Row refresh cyc time (Trfc) - 16 Bus Clocks

Row to Row delay (Trrd) - 04 Bus Clocks

Write recovery time (Twr) - 04 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 4708 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Decrease

DQS Skew Value - 0

DRAM Drive Strength - weak4 (level 7)

DRAM Data Drive Strength - 3

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Normal

Read Preamble Time - 6.0 Nano Seconds (this causes errors at 5)

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 04 x

32 Byte Granularity - Disable(4 Bursts)

 

memtest 5 400passes with 30 errors (almost stable but gave up and went with tight 260)

- Didnt bother with prime

- I had a 120mm fan over the ram aswell.

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Motherboard: DFI LanParty NF4 Ultra-D

CPU: AMD Opteron 144 (CAB2E 0542EPMW)

RAM: 2x1GB G.Skill PC4000 (F1-4000USU2-2GBHZ)

BIOS: 623-1

 

FSB Bus Frequency - 260

LDT/FSB Frequency Ratio - 4

CPU/FSB Frequency Ratio - 9

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - AUTO

 

CPU VID Control - auto

CPU VID Special Control - Auto

LDT Voltage Control - 1.20v

Chip Set Voltage Control - 1.50v

DRAM Voltage Control - 2.6v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 7 Bus Clocks

Row refresh cyc time (Trfc) - auto

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS# latency (tWCL) - auto

DRAM Bank Interleave - Enabled

 

DQS Skew Control - auto

DQS Skew Value - 0

DRAM Drive Strength - auto

DRAM Data Drive Strength - auto

Max Async Latency - auto

DRAM Response Time - Normal

Read Preamble Time - auto

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

Memtest 86+

Pass:

Test 5: 8h

Test 8: 1h 30min

Some results: www.majsormar.se/oc/ram.htm

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OK...i have gone back to the drawing board......lol

 

 

it seems that, being stable 1:1 is alot easier than stable on a divider. For instance. I can get stable 1:1 all the way to 277mhz.....but i have yet to find a good stable setting for anything over 250 on a divider........WTH am i doing wrong?

 

Here are my current settings:

 

Motherboard: DFI LanParty NF4 Ultra-D

CPU: AMD Opteron 165 CCB1E 0550VPMW

RAM: 2x1GB G.Skill PC4000 (F1-4000USU2-2GBHZ)

BIOS: 704-2BTA

 

FSB Bus Frequency - 270

LDT/FSB Frequency Ratio - 3

CPU/FSB Frequency Ratio - 9

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - AUTO

 

CPU VID Control - auto

CPU VID Special Control - Auto

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.50v

DRAM Voltage Control - 2.5v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 10 Bus Clocks

Row refresh cyc time (Trfc) - 14 clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3684 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - auto

DQS Skew Value - 0

DRAM Drive Strength - weak3

DRAM Data Drive Strength - level 1

Max Async Latency - 9

DRAM Response Time - normal

Read Preamble Time - 6

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

 

 

I have tried just about every combanation i have seen.........nothing seems to be stable in prime95x2 on a divider.

 

I need some help bad!!

 

CJ

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OK...i have gone back to the drawing board......lol

 

 

it seems that, being stable 1:1 is alot easier than stable on a divider. For instance. I can get stable 1:1 all the way to 277mhz.....but i have yet to find a good stable setting for anything over 250 on a divider........WTH am i doing wrong?

 

I have tried just about every combanation i have seen.........nothing seems to be stable in prime95x2 on a divider.

 

I need some help bad!!

 

CJ

 

CPU VID Control - 3.75 or 4

CPU VID Special Control - Auto

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.60v

DRAM Voltage Control - 2.6v

 

Row to Row delay (Trrd) - 04 Bus Clocks

Try that

 

 

Also spennis, maybe you should let us know if urs work for more than 2hrs stable.

Like 8hours in memtest5 and 8hrs dual prime95 and a superpi 1mb run :D

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hey guys, i found that using test 8, i can spot error better.... my Gold XTC pc4000 can run up to 286 memtest5-only stable for a few hours, but lots of errors on test 8, found out when i try to do the whole thing. since then i test with 8 first, if it pass twice on 8, then i'll go ahead to test 5 for acouple of hours, or skip it alltogether to run prime.... wadaya think?

 

my XTC can go sometime above 267 but i never use it coz with my HTT at 311, my divider gives it 257

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Hmm, maybe both i would use, or even all of them. But to just see if your stable and trying to get high OC 30mins of each would be enough. Then if you want to stay where you are and tighten timings, lower volts then you do 8 hours each.

I am happy with 2600ghz and 260htt with tight timings. To get to 2700 and 270 is not that much performance increase but way high volts (1.325,1.375-> 1.55,1.6) its not worth it.

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Also spennis, maybe you should let us know if urs work for more than 2hrs stable.

Like 8hours in memtest5 and 8hrs dual prime95 and a superpi 1mb run :D

 

I haven't tested them for that long yet. I'll try test 5 for a longer period of time. Do you mean that I should run 2x Prime 95 and superPi 1mb at the same time? How do I start two different Prime 95 at the same time?

 

I'm sure of one thing though. Changing the Dram voltage didn't help at all. In fact running at 2,5v seems to work just as fine as 2,6->2,8v.

 

EDIT: I have now been running memtest, test 5 for 8 hours @ 260 MHz 2,6v (without any errors, of course). I've also updated my earlier post.

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OK update

 

Motherboard: DFI LanParty UT SLI-DR Expert

CPU: AMD Athlon 64 Vinece 3200+

MEM: 2x1GB G.Skill PC4000 (F1-4000USU2-2GBHZ)

BIOS: 12/7/05

 

FSB Bus Frequency - 250

LDT/FSB Frequency Ratio - 4

CPU/FSB Frequency Ratio - 8

PCI eXpress Frequency - 100Mhz

 

CPU VID StartUp Value - AUTO

 

CPU VID Control - auto

CPU VID Special Control - Auto

LDT Voltage Control - 1.30v

Chip Set Voltage Control - 1.62v

DRAM Voltage Control - 2.71v

 

DRAM Configuration Settings:

 

DRAM Frequency Set - 200 = RAM/FSB 1:1

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 03

RAS# to CAS# delay (Trcd) - 04 Bus Clocks

Min RAS# active time (Tras) - 08 Bus Clocks

Row precharge time (Trp) - 04 Bus Clocks

Row Cycle time (Trc) - 13 Bus Clocks

Row refresh cyc time (Trfc) - 16 clocks

Row to Row delay (Trrd) - 04 Bus Clocks

Write recovery time (Twr) - 03 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 4708 Cycles

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Decrease

DQS Skew Value - 0

DRAM Drive Strength - weak7

DRAM Data Drive Strength - level 3

Max Async Latency - 8

DRAM Response Time - normal

Read Preamble Time - 6

IdleCycle Limit - 256 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

 

with this I was prime 95 stable ran for 12 1/2 hrs

memtest 16 full passes i had only 8 errors 2 each on pass 1, 9, 11, 13 on test 5

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OK update

 

 

with this I was prime 95 stable ran for 12 1/2 hrs

memtest 16 full passes i had only 8 errors 2 each on pass 1, 9, 11, 13 on test 5

 

you shouldnt have any errors at all on memtest...

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