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G.Skill HZ/Any other UCCC (2x1024) 260+ please post here


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#25 Clint

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Posted 09 February 2006 - 10:21 AM

same chips but different PCB will produce different results will it not? Otherwise everyone would be buying up ADATA UCCC chips, correct?


Ok, so you suggesting I remove it then?

#26 Evancold

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Posted 09 February 2006 - 10:27 AM

Don't get me wrong, all I am trying to say is that they may not perform the same as the G Skill HZ sticks. Was just wondering if that would defeat the purpose of this thread or not, but that is not my decision. :D But very nice clock you have on those sticks.

#27 Clint

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Posted 09 February 2006 - 10:32 AM

No prob

..lets just see what will come out of it ;)

#28 Burky

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Posted 09 February 2006 - 10:46 AM

my sticks are running memtest fine at default settings at 250mhz, but they won't do 260mhz even if I go to 2.8v from 2.6v.

Please give me some ideas here. This is hindering my oc.

#29 blick

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Posted 09 February 2006 - 11:04 AM

Anyway, I can't get memtest to pass more than 20%, even when I up the voltage to 2.8V, and that sucks.

Burky try at 2.5v, this UCCC love low voltage not high.


These are my settings:

FSB Bus Frequency - 260
LDT/FSB Frequency Ratio - AUTO
CPU/FSB Frequency Ratio - AUTO
PCI eXpress Frequency - 100Mhz
CPU VID StartUp Value - 1.450v
CPU VID Control - 1.450v
CPU VID Special Control - Above VID * 110%
LDT Voltage Control - 1.20v
Chip Set Voltage Control - 1.50v
DRAM Voltage Control - 2.50v


DRAM Frequency Set - 200=RAM/FSB:01/1
Command Per Clock (CPC) - Enable
CAS Latency Control (Tcl) - 3.0
RAS# to CAS# delay (Trcd) - 04 Bus Clocks
Min RAS# active time (Tras) - 07 Bus Clocks
Row precharge time (Trp) - 04 Bus Clocks
Row Cycle time (Trc) - 07 Bus Clocks
Row refresh cyc time (Trfc) - 13 Bus Clocks
Row to Row delay (Trrd) - 02 Bus Clocks
Write recovery time (Twr) - 02 Bus Clocks
Write to Read delay (Twtr) - 01 Bus Clocks
Read to Write delay (Trwt) - 03 Bus Clocks
Refresh Period (Tref) - 3684 Cycles
Write CAS Latency (Twcl) - 1 clk
DRAM Bank Interleave - Enabled

DQS Skew Control - Auto
DQS Skew Value - 0
DRAM Drive Strength - Auto
DRAM Data Drive Strength - Auto
Max Async Latency - 7.0 Nano Seconds
DRAM Response Time - Normal
Read Preamble Time - 5.0 Nano Seconds
IdleCycle Limit - 256 Cycles
Dynamic Counter - Enable
R/W Queue Bypass - 16 x
Bypass Max - 07 x
32 Byte Granularity - Disable(4 Bursts)

Stop at 260 because my 3200+ Venice hit the wall :( so no point to struggle...

#30 Guest_FZ1_*

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Posted 09 February 2006 - 11:12 AM

updated table/picture on 02/09/2006 10.35 am (eastern).

@FZ1: 9x317 / 11 = 259 mhz not 269. 11 comes from: 9x(6/5) = 10.8 >>> 11(other peoples "real ram mhz" calculated by using this formula.)

Sorry, typo there

#31 Burky

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Posted 09 February 2006 - 11:25 AM

Thanks a lot Blick, same with my Venice too, so I'm happy if I can make 260 stable though I'm trying to push 2.7ghz as soon as I get my ram sorted.

#32 tdntx

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Posted 09 February 2006 - 11:28 AM

Stop at 260 because my 3200+ Venice hit the wall :( so no point to struggle...

Same here. My X2 can run stable 250x11 or 270x10 but only with 1.6v vcore. I don't feel comfortable running 24/7 with that high vcore on air considering the questionable CPU temp reading (Idle 22C Dual Prime 36C Ambient Room 22C).

#33 blick

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Posted 09 February 2006 - 11:28 AM

Thanks a lot Blick, same with my Venice too, so I'm happy if I can make 260 stable though I'm trying to push 2.7ghz as soon as I get my ram sorted.

good luck!

#34 Burky

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Posted 09 February 2006 - 11:32 AM

Just out of curiousity, is there a particular BIOS best for these sticks here?
I'm using OCZ Tony's one now, but in terms of performance between the 2nd and 3rd 6/23 BIOs I can't notice any difference.

#35 blick

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Posted 09 February 2006 - 11:41 AM

I've read somewhere that 623-1 is good, but I didn't try other BIOSes so I can't tell you for sure

#36 Burky

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Posted 09 February 2006 - 11:48 AM

Ok. well it failed after 7% on the settings you have blick, so I'm not sure where to go from here. Shall I try the 623-1 BIOS instead do you think?