3dMark01 crashing at OC

[Guest Ryn]

I was able to reach 2.5Ghz on my X2 (10x250) using the 180 dividers on the mem and feeding it with 3.2V. I can run and pass 2 instances of SuperPI 32M. I also passed 2 instances of Prime95 for 10hrs and 10hrs on memtest. I can also pass 3dmark03 and 05 and run looping tests. I'm wondering why I always error on 3dmark01. While fiddling with my setup, I got a BSOD on my system stating nv4_dll or something similar. I then used the 150 divider on the mems and after that I ran 3dmark01 again and it passed and I even ran 3 tests after that. So I can safely assume that it is the settings on my mems. Can you guys help me out with my ram settings for BH5? Thanks in advance.

[wevsspot]

Are you overclocking your video card as well?

 

As for BIOS and memory settings for your BH5, visit the Socket939 Overclocking Database, find CPU and memory similar to yours and borrow those timings. The settings there are confirmed toaster stable, and it's a good starting point. You can find the thread here;

 

http://www.dfi-street.com/forum/showthread.php?t=10195

[Guest Ryn]

The video card still running on its stock factory setting (445/1070). I might try those setting but I think the Data Drive Strength on the Expert is a bit different compared to the previous NF4 mobos which is getting me a bit confused. Most eperts on the OC database and Stock speed database are using TCCC or other similar RAM's that uses low voltage and looser timings like TCCD's.

[Guest Ryn]

BTW, here are the settings of my ram @ 10x250:

 

DRAM Frequency Set - 180=RAM/FSB:09/10

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2

RAS# to CAS# delay (Trcd) - 2 Bus Clocks

Min RAS# active time (Tras) - 8 Bus Clocks

Row precharge time (Trp) - 2 Bus Clocks

Row Cycle time (Trc) - 09 Bus Clocks

Row refresh cyc time (Trfc) - 15 Bus Clocks

Row to Row delay (Trrd) - 02 Bus Clocks

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - 1

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto

DQS Skew Value - 0

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 1

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 7.0 Nano Seconds

IdleCycle Limit - 032 Cycles

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)

[wevsspot]

I've added my recommendations in blue

 

BTW, here are the settings of my ram @ 10x250:

 

DRAM Frequency Set - 180=RAM/FSB:09/10

Command Per Clock (CPC) - Enable

CAS Latency Control (Tcl) - 2

RAS# to CAS# delay (Trcd) - 2 Bus Clocks

Min RAS# active time (Tras) - 8 Bus Clocks

Row precharge time (Trp) - 2 Bus Clocks

Row Cycle time (Trc) - 9 Bus Clocks 8

Row refresh cyc time (Trfc) - 15 Bus Clocks 16

Row to Row delay (Trrd) - 02 Bus Clocks 3

Write recovery time (Twr) - 02 Bus Clocks

Write to Read delay (Twtr) - 02 Bus Clocks

Read to Write delay (Trwt) - 03 Bus Clocks

Refresh Period (Tref) - 3120 Cycles

Write CAS Latency (Twcl) - 1

DRAM Bank Interleave - Enabled

 

DQS Skew Control - Auto Increase

DQS Skew Value - 0 50

DRAM Drive Strength - Level 8

DRAM Data Drive Strength - Level 2

Max Async Latency - 8.0 Nano Seconds

DRAM Response Time - Fast

Read Preamble Time - 7.0 Nano Seconds 6.0

IdleCycle Limit - 032 Cycles 128 or 256

Dynamic Counter - Disable

R/W Queue Bypass - 16 x

Bypass Max - 07 x

32 Byte Granularity - Disable(4 Bursts)