mxrider750 Posted October 18, 2005 Posted October 18, 2005 I oc'ed my X2 +3800 to 2.5ghz... I primed both cores, core 0 was stable, while core 1 had fatal errors. What does this mean? Do i need to up the vcore to make core1 stable? Share this post Link to post Share on other sites More sharing options...
Pyr0 Posted October 18, 2005 Posted October 18, 2005 probably Share this post Link to post Share on other sites More sharing options...
timhaas1 Posted October 28, 2005 Posted October 28, 2005 Thought I'd post my OC results on the off chance that someone might find it useful. My 4400+ has been running at 2.75GHz per core for the last two weeks - 250 FSB 11X Multiplier 2750 MHz @ 2-3-3-8 RAM settings. I've even been gaming, downloading, and converting tons of video like a fiend too - often at the same time. I'm not using the supplemental power inputs on the MOBO, but I have had to compensate for initial dips in power on the 12 volt and 5 volt rails using the True Control front panel. Though I set the chip at 1.45 volts in BIOS, Smart Guardian reads the voltage at 1.55. I included my BIOS settings below. Temps after several hours of Quake4 while downloading at the same time have never been over 39C. Tends to run idle at 33C and 36-38C under load. Maybe I just got lucky. My Rig: DFI LanParty NF4 Ultra-D (SLI Mod) AMD Athlon64 X2 4400+ 2X512MB OCZ DDR500 PC4000 Gold VX 2-3-3-8 at 3.3 volts Swiftech Watercooling w/ Reservoir Chieftec Dragon Tower Modified with a 120mm fan in the top of case Antec "True Control" 550 (using 20-pin to 24-pin conversion cable) 80GB & 300GB Seagate Barracuda SATA BFG 7800 GT OC (Detonator 77.77 & 81.85) Windows XP Pro (Service Pack 2) My Genie BIOS Settings: FSB Bus Frequency - 250 LDT/FSB Frequency Ration - Auto CPU/FSB Frequency Ratio - Auto PCI eXpress Frequency - 100Mhz CPU VID StartUp Value - StartUp CPU VID Control - 1.450v CPU VID Special Control - Avove VID * 110% LDT Voltage Control - 1.20v Chip Set Voltage Control - 1.50v DRAM Voltage Control - 3.40v DRAM Configuration Settings: DRAM Frequency Set - AUTO (DRAM/FSB:1/01) Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2 RAS# to CAS# delay (Trcd) - 03 Bus Clocks Min RAS# active time (Tras) - 08 Bus Clocks Row precharge time (Trp) - 03 Bus Clocks Row Cycle time (Trc) - AUTO Row refresh cyc time (Trfc) - AUTO Row to Row delay (Trrd) - AUTO Write recovery time (Twr) - AUTO Write to Read delay (Twtr) - AUTO Read to Write delay (Trwt) - AUTO Refresh Period (Tref) - 3120 Cycles Write CAS Latency (Twcl) - Auto DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - AUTO DRAM Data Drive Strength - AUTO DRAM Response Time - Normal Max Async Latency - Auto Read Preamble Time - Auto IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity – Disable (4 Bursts) Share this post Link to post Share on other sites More sharing options...
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