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Supercharged

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Everything posted by Supercharged

  1. danger den tdx cool-trek Dp1202 laing d5 pump i tried to lower the HTT bit by bit to see the stable point so far i;ve gotten to 2.85Ghz. at 1.65vcore. i noticed if i primed core2 then prime core 1 a few seconds apart, then it would fail within minutes. but if i start priming core 1. then after it passes the test 1 (which is a few mins later) start priming core 2, prime95 can go on without errors for 2hrs plus before failing. the max this chip can go is 3.05Ghz. that is failing occt(not to mention prime95) on stock vcore, it can reach 2.7ghz and pass occt though i didnt try prime95 before attempting higher clock speeds.
  2. any suggestions ? i'm already in an air-conditioned room, 2x120mm rad,
  3. core 2 on the left core 1 on the right
  4. guys for the Dram settings, shld i be using the NF4 guide or the ones frm GSkill 2GBkits user thread since i am using those rams? another thing is, i realised i am testing dram settings and cpu vcore/fsb at the same time. now can i say that dram settings for a ocdb stable 2.5ghz for example, can work for a 2.8GHz overclock? assuming the vcore for 2.8Ghz is stable.
  5. now i raised the vcore slightly from 1.5x 109.6% to 112% and the reverse happens??? i mean both cores under prime at 1.65vcore shld they be hot?
  6. FSB Bus Frequency............................. - 300 LDT/FSB Frequency Ratio....................... - 3x CPU/FSB Frequency Ratio....................... - 10x PCI eXpress Frequency......................... - 105Mhz CPU VID StartUp Value......................... - 1.500v CPU VID Control............................... - 1.500v CPU VID Special Control....................... - 109.6% LDT Voltage Control........................... - 1.40v Chip Set Voltage Control...................... - 1.52v DRAM Voltage Control.......................... - 2.68v DRAM Configuration Settings: DRAM Frequency Set............................ - 10 Command Per Clock (CPC)....................... - Enable CAS Latency Control (Tcl)..................... - 3 RAS# to CAS# delay (Trcd)..................... - 4 Min RAS# active time (Tras)................... - 8 Row precharge time (Trp)...................... - 3 Row Cycle time (Trc).......................... - 11 Bus Clocks Row refresh cyc time (Trfc)................... - 16 Bus Clocks Row to Row delay (Trrd)....................... - 02 Bus Clocks Write recovery time (Twr)..................... - 03 Bus Clocks Write to Read delay (Twtr).................... - 01 Bus Clocks Read to Write delay (Trwt).................... - 03 Bus Clocks Refresh Period (Tref)......................... - 4128 Cycles DRAM Bank Interleave.......................... - Enabled DQS Skew Control.............................. - auto DQS Skew Value................................ - 0 DRAM Drive Strength........................... - level 7 DRAM Data Drive Strength...................... - 3 Max Async Latency............................. - 8.0ns DRAM Response Time............................ - Normal Read Preamble Time............................ - 5ns IdleCycle Limit............................... - 16 Cycles Dynamic Counter............................... - Disable R/W Queue Bypass.............................. - 16 x Bypass Max.................................... - 07 x 32 Byte Granularity........................... - Disable(4 Bursts) i am running these settings at 2.88Ghz and like what happened before i lower fsb from 290 to 288, core 1 failed pretty soon. currently core 1 lasted till Test2 before failing while core 2 goes on strong! before i lowered the fsb frm 290 to 288, core 1 would only last till Test 1 before failing but core 2 goes on strong/ max temps for both cores running is 56-58degC
  7. FSB Bus Frequency............................. - 300 LDT/FSB Frequency Ratio....................... - 3x CPU/FSB Frequency Ratio....................... - 10x PCI eXpress Frequency......................... - 101Mhz CPU VID StartUp Value......................... - 1.500v CPU VID Control............................... - 1.400v CPU VID Special Control....................... - 116.8% LDT Voltage Control........................... - 1.20v Chip Set Voltage Control...................... - 1.52v DRAM Voltage Control.......................... - 2.68v DRAM Configuration Settings: DRAM Frequency Set............................ - 10 Command Per Clock (CPC)....................... - Enable CAS Latency Control (Tcl)..................... - 3 RAS# to CAS# delay (Trcd)..................... - 4 Min RAS# active time (Tras)................... - 8 Row precharge time (Trp)...................... - 4 Row Cycle time (Trc).......................... - 13 Bus Clocks Row refresh cyc time (Trfc)................... - 16 Bus Clocks Row to Row delay (Trrd)....................... - 03 Bus Clocks Write recovery time (Twr)..................... - 03 Bus Clocks Write to Read delay (Twtr).................... - 02 Bus Clocks Read to Write delay (Trwt).................... - 03 Bus Clocks Refresh Period (Tref)......................... - 3120 Cycles DRAM Bank Interleave.......................... - Enabled DQS Skew Control.............................. - Increase Skew DQS Skew Value................................ - 221 DRAM Drive Strength........................... - Level 8 DRAM Data Drive Strength...................... - Auto Max Async Latency............................. - 8.0ns DRAM Response Time............................ - Normal Read Preamble Time............................ - 5.5ns IdleCycle Limit............................... - 128 Cycles Dynamic Counter............................... - Disable R/W Queue Bypass.............................. - 16 x Bypass Max.................................... - 07 x 32 Byte Granularity........................... - Disable(4 Bursts) currently testing diff settings used by some of the 3Ghz members. this current settings rebooted when showing the windows loading screen but was able to boot normally after that.
  8. the settings passed memtest but refused to boot into windows. reboots at the windows scrolling bars "screen"
  9. i see... i am using 9/6.5 . MAL must be 8 or 9 before i can even boot. thanks
  10. err..looser ? as in 200,166,150 needs to be loosen mal/rp? abit confused with the relative terms ooops
  11. twtr is set at 02. if i set it to 01, how much is it gonna affect the stability. how many memtest passes are we talking abt ? test5 right?
  12. divider of 100 is just for cpu oc. but when i set proper dividers between max cpu oc and rams oc then wouldnt it be different?
  13. in other words, tweaking the dram settings isnt going to make the cpu more stable ? and now the only thing left is the vcore? so if raising the vcore isnt going to help make it stable means it simply isnt stable at 3GHz?
  14. just want to know whether dram settings are linked to CPU overclocking because i am trying to make my 3ghz oc stable so tweaking the dram settings dont seem to help. so just wondering.. thanks
  15. BIOS Settings: FSB Bus Frequency............................. - 300 LDT/FSB Frequency Ratio....................... - 4 CPU/FSB Frequency Ratio....................... - 10 PCI eXpress Frequency......................... - 105 CPU VID StartUp Value......................... – 1.425 CPU VID Control............................... – 1.4 CPU VID Special Control....................... – 114.4% LDT Voltage Control........................... – 1.3 Chip Set Voltage Control...................... - 1.59 DRAM Voltage Control..........................- 2.6 DRAM Configuration Settings: DRAM Frequency Set............................ - 100 Command Per Clock (CPC).......................- enable CAS Latency Control (Tcl)..................... – 3 RAS# to CAS# delay (Trcd)..................... - 4 Min RAS# active time (Tras)................... - 8 Row precharge time (Trp)...................... - 3 Row Cycle time (Trc).......................... - 7 Row refresh cyc time (Trfc)................... - 14 Row to Row delay (Trrd)....................... - 02 Write recovery time (Twr)..................... - 02 Write to Read delay (Twtr).................... - 02 Read to Write delay (Trwt).................... - 03 Refresh Period (Tref)......................... - 3120 DRAM Bank Interleave.......................... - enable DQS Skew Control.............................. - auto DQS Skew Value................................ - 0 DRAM Drive Strength........................... -7 DRAM Data Drive Strength...................... - 4 Max Async Latency............................. - 12 DRAM Response Time............................ - normal Read Preamble Time............................ – 5.5 IdleCycle Limit............................... - 128 Dynamic Counter............................... - enable R/W Queue Bypass.............................. – 16x Bypass Max.................................... – 7x 32 Byte Granularity........................... – 4bursts still unstable.:mad:
  16. i read some ppl alter the max async latency and the read preamble time to make it stable. but do u increase or decrease these values ?
  17. for my opteron170, which shld i use ? prime 95(2 copies). sp2004(2 copies) or orthos??
  18. i just had an idea. not sure how would this work. sometimes ppl raise the vcore by abit to make their oc stable and the max safe vcore for 90nm cpus are 1.6-1.65vcore. so i was thinking, is it ok to say set a vcore say, 1.6v then follow the steps in the oc guide to get the max oc rather than overclock with a certain vcore then slowly lower the oc ???
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