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Supercharged

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Everything posted by Supercharged

  1. guys if my cpu is stable for say 8hrs but fails at the 12th hr, is it stable or not?
  2. guys i;ve got a question. to use this cd, i must reboot and set bios to boot with cd first then i get the menu right?
  3. guys i;ve got a question. to use this cd, i must reboot and set bios to boot with cd first then i get the menu right?
  4. problem is i am still testing the settings for my 3ghz. i mean i really dont know how to try once i add another variable into the equation. i mean, maybe the bios is right for me but it's the settings that are making it unstable ? and vice versa? does it show any visible increment in stability when the bios is changed?
  5. has anyone changed the bios just to stabilise their OC? i'm uncertain whether to do so because i'm not sure whether does it help at all. thanks
  6. impossible as in unstable settings ? even on the same settings, sometimes i get success and sometimes i dont. for DDS, the guide mentioned something abt tccd working better with weak, DDS. rams frm ocz suited to 6 or 8 then waht abt UCCC rams?
  7. guys waht shld i set for DDS/DDDS and idle cycle limit ? i've tried and tried for weeks and they dont seem to help. i remember DDDS setting to HI for high dram loads or stabilise overclocked system. i mean, just checking, only th cpu is overclocked, not the rams, it's the same right? btw waht's verifying pool data ? sometimes i get success sometimes i dont.
  8. another thing i am worried is that whether the difference in timings will cause any instability or not since other settings will change once the timings are different too.
  9. since i am just oc my cpu and leaving my rams on a divider, i still tweak the dram idle timer etc at the dram settings as well? 1 thing, my rams are 2.5-3-3-6 for 200mhz but the dividers and fsb speeds makes the rams run at 200mhz but when i was tweaking the dram settings, i changed the timings to 3-4-4-8. is this going to cause any issues ? i mean after oc the cpu and making it stable, i plan to oc the rams as well... thanks
  10. 1 thing to note. i am not trying to oc my rams yet. just oc my cpu. so the rams are under a 133mhz divider which basically makes it run near to 200mhz(stock speeds) the timings i use is 3-4-4-8 for this speed but the stock timings are 2.5-3-3-6 for 200mhz. does it make a difference?
  11. does anyone know waht has DQS skew control, dqs value, DDS, DDDS etc. have on oc ????
  12. guys...any ideas ? i've tried tweaking the MAL, RPT, tref, data drive strengths, etc. but i cant even get 2.95 stable. i'm already at 1.68vcore. idle temps at 31degC load 45degC max
  13. FSB Bus Frequency............................. - 300 LDT/FSB Frequency Ratio....................... - 3x CPU/FSB Frequency Ratio....................... - 10x PCI eXpress Frequency......................... - 100Mhz CPU VID StartUp Value......................... - 1.500v CPU VID Control............................... - 1.2250v CPU VID Special Control....................... - 136.0% LDT Voltage Control........................... - 1.40v Chip Set Voltage Control...................... - 1.62v DRAM Voltage Control.......................... - 2.71v DRAM Configuration Settings: DRAM Frequency Set............................ - 10 Command Per Clock (CPC)....................... - Enable CAS Latency Control (Tcl)..................... - 3 RAS# to CAS# delay (Trcd)..................... - 4 Min RAS# active time (Tras)................... - 8 Row precharge time (Trp)...................... - 4 Row Cycle time (Trc).......................... - 13 Bus Clocks Row refresh cyc time (Trfc)................... - 15 Bus Clocks Row to Row delay (Trrd)....................... - 03 Bus Clocks Write recovery time (Twr)..................... - 03 Bus Clocks Write to Read delay (Twtr).................... - 02 Bus Clocks Read to Write delay (Trwt).................... - 03 Bus Clocks Refresh Period (Tref)......................... - 3120 Cycles DRAM Bank Interleave.......................... - Enabled DQS Skew Control.............................. - increase DQS Skew Value................................ - 221 DRAM Drive Strength........................... - level 8 DRAM Data Drive Strength...................... - auto Max Async Latency............................. - 9.0ns DRAM Response Time............................ - Normal Read Preamble Time............................ – 7.5ns IdleCycle Limit............................... - 128 Cycles Dynamic Counter............................... - Disable R/W Queue Bypass.............................. - 16 x Bypass Max.................................... - 07 x 32 Byte Granularity........................... - Disable(4 Bursts)
  14. another thing, does the time it takes to fail prime95 mean anything? whether it takes 1min or 5mins means i am getting closer ? i noticed there are a few errors when an OC fails prime95, 1. rounding was 0.453432, expected less than 0.4 2. rounding was 0.5 3. "100 errors" does anyone of the errors mean tht u are 'closer' to a stable overclock ?
  15. seriously i still dont understand after reading the trefs thread. i simply dont understand what is wrong and what else shld i change. MAL and RPT ?
  16. seriously i still dont understand after reading the trefs thread. i simply dont understand what is wrong and what else shld i change. MAL and RPT ?
  17. i mean, i looked at dracula's table and tried the trefs values corresponding to my dividers but it still isnt stable. i even tried all the trefs on the table and the best i've got is 2hrs stable max.
  18. erm can someone give me a hand with the trefs ? i;ve tried every tref possible and tweaked the MAL and RPT. still no go.
  19. FSB Bus Frequency............................. - 300 LDT/FSB Frequency Ratio....................... - 3x CPU/FSB Frequency Ratio....................... - 10x PCI eXpress Frequency......................... - 100Mhz CPU VID StartUp Value......................... - 1.500v CPU VID Control............................... - 1.500v CPU VID Special Control....................... - 109.6% LDT Voltage Control........................... - 1.40v Chip Set Voltage Control...................... - 1.62v DRAM Voltage Control.......................... - 2.71v DRAM Configuration Settings: DRAM Frequency Set............................ - 10 Command Per Clock (CPC)....................... - Enable CAS Latency Control (Tcl)..................... - 3 RAS# to CAS# delay (Trcd)..................... - 4 Min RAS# active time (Tras)................... - 8 Row precharge time (Trp)...................... - 4 Row Cycle time (Trc).......................... - 13 Bus Clocks Row refresh cyc time (Trfc)................... - 15 Bus Clocks Row to Row delay (Trrd)....................... - 03 Bus Clocks Write recovery time (Twr)..................... - 03 Bus Clocks Write to Read delay (Twtr).................... - 02 Bus Clocks Read to Write delay (Trwt).................... - 03 Bus Clocks Refresh Period (Tref)......................... - 3120 Cycles DRAM Bank Interleave.......................... - Enabled DQS Skew Control.............................. - increase DQS Skew Value................................ - 221 DRAM Drive Strength........................... - level 8 DRAM Data Drive Strength...................... - auto Max Async Latency............................. - 9.0ns DRAM Response Time............................ - Normal Read Preamble Time............................ – 7.5ns IdleCycle Limit............................... - 128 Cycles Dynamic Counter............................... - Disable R/W Queue Bypass.............................. - 16 x Bypass Max.................................... - 07 x 32 Byte Granularity........................... - Disable(4 Bursts) i;ve already increased RPT to 7.5ns and tried every tref values and the best i've got is 3hrs prime stable for core 2.
  20. guys i need some help here... just cant get it 3.0ghz stable at all... tried boosting vcore to 1.66 and some minor changes to the 2.9ghz stable ones but fails prime within a min...
  21. yes...think i didnt include this in, the dividers are 120mhz
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