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tmd5

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  1. DFI LANPARTY nF4 ultra-d - 5/10FIX-1 BIOS AMD Athlon 64 3000+ Venice Socket 939 Processor Model - YBBLE 0523 DPAW stepping 2x512MB OCZ EL Platinum revision 2 V1.1 TCC5 memory Leadtek 6800GT 256MB GDDR3 PCI-Express, Dual DVI-I ---> 7.7.7.2 - @415/1115 1x Western Digital WD800JB 80GB IDE 8MB 7200RPM Pioneer- DVD-ROM DVD-115 Hiper Type-R 580W blue Arctic Freezer 64 copper heatpipe heatsink/fan ====================== Genie BIOS Settings: FSB Bus Frequency - 280 LDT/FSB Frequency Ration - x3 CPU/FSB Frequency Ratio - x9 PCI eXpress Frequency - 100Mhz CPU VID StartUp Value - 1.5v CPU VID Control - 1.3v CPU VID Special Control - Avove VID * 126% LDT Voltage Control - 1.20v Chip Set Voltage Control - 1.50v DRAM Voltage Control - 2.7v DRAM Configuration Settings: DRAM Frequency Set - 200 (DRAM/FSB:1/01) Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2.5 RAS# to CAS# delay (Trcd) - 04 Bus Clocks Min RAS# active time (Tras) - 08 Bus Clocks Row precharge time (Trp) - 03 Bus Clocks Row Cycle time (Trc) - 10 Bus Clocks Row refresh cyc time (Trfc) - 18 Bus Clocks Row to Row delay (Trrd) - 03 Bus Clocks Write recovery time (Twr) - 03 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trtw) - 03 Bus Clocks Refresh Period (Tref) - 4708 Cycles Write CAS Latency (Twcl) - Auto DRAM Bank Interleave - Enabled DQS Skew Control - Slower DQS Skew Value - 128 DRAM Drive Strength - Level 7 DRAM Data Drive Strength - Level 3 Max Async Latency - 8ns Read Preamble Time - 7ns IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(4 Bursts) ==================== Prime95 + 3dMark2001SE + CPU-Z 1.26 + Everest 1.51: http://img343.imageshack.us/my.php?image=ocprime3d14gv.jpg 3dMark2003: 3dMark2005: Aquamark 3d: ====================== short description: 280x9 @ 2520Mhz, 1.3v + 126% 2.5-4-8-3 @ 2.7v vdimm
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