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xinty

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  1. anyone? i need to know also. waiting to shift my vga to 2nd slot.
  2. xinty

    DRAM response speed

    if u set Max Async Latency and Read Preamble Time manually. DRAM Response Time can leave it as AUTO. correct me if i m wrong.
  3. xinty

    Memory timings headache.........

    try to input more info, such as memory configuration setting in bios. so pro here can help. maybe your memory respond is too high, try normal.
  4. Finally my cheapo rig. can do something that make me pround :shake: if have anything to improve pls kindly let me know. 10x.
  5. DFI LANPARTY nF4 D - 7/04-2 BigToe BIOS AMD Athlon64 3000+ Venice 2 x 512MB Patriot Signiture Line (UTT) Xpertvision [email protected]/1200 128MB DDR3 (not GT) Hitachi 80GB Sata hdd (8MB cache) Acbel I-Power 400W Power Supply (3.3v rail mod) Genie BIOS Settings: FSB Bus Frequency - 300 LDT/FSB Frequency Ratio - 3 CPU/FSB Frequency Ratio - 9 PCI eXpress Frequency - 100Mhz CPU VID StartUp Value - StartUp CPU VID Control - 1.500v CPU VID Special Control - Above VID * 113% LDT Voltage Control - 1.30v Chip Set Voltage Control - 1.60v DRAM Voltage Control - 3.40v (Bios show 3.36v) DRAM Configuration Settings: DRAM Frequency Set - 166 Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2 RAS# to CAS# delay (Trcd) - 02 Bus Clocks Min RAS# active time (Tras) - 05 Bus Clocks Row precharge time (Trp) - 02 Bus Clocks Row Cycle time (Trc) - 07 Bus Clocks Row refresh cyc time (Trfc) - 16 Bus Clocks Row to Row delay (Trrd) - 03 Bus Clocks Write recovery time (Twr) - 03 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trwt) - 03 Bus Clocks Refresh Period (Tref) - Auto DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - Auto DRAM Data Drive Strength - Auto Max Async Latency - 8.0 Nano Seconds DRAM Response Time - Fast Read Preamble Time - 6.0 Nano Seconds IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(4 Bursts) 3dMark2003: 3dMark2005: short description: 300x9 @ 2700Mhz, 1.500v + 113% 2-2-5-2 @ 3.4v vdimm (Bios show 3.36v)
  6. in my experience, if i get error7 i able to solve it with setting the vdimm a step higher.
  7. try this: Command Per Clock (CPC) - Enable CAS Latency Control (Tcl) - 2 RAS# to CAS# delay (Trcd) - 02 Bus Clocks Min RAS# active time (Tras) - 06 Bus Clocks Row precharge time (Trp) - 02 Bus Clocks Row Cycle time (Trc) - 08 Bus Clocks Row refresh cyc time (Trfc) - 16 Bus Clocks Row to Row delay (Trrd) - 03 Bus Clocks Write recovery time (Twr) - 03 Bus Clocks Write to Read delay (Twtr) - 02 Bus Clocks Read to Write delay (Trwt) - 03 Bus Clocks Refresh Period (Tref) - auto DRAM Bank Interleave - Enabled DQS Skew Control - Auto DQS Skew Value - 0 DRAM Drive Strength - Auto DRAM Data Drive Strength - Auto Max Async Latency - 9.0 Nano Seconds DRAM Response Time - Fast Read Preamble Time - 6.0 Nano Seconds IdleCycle Limit - 256 Cycles Dynamic Counter - Disable R/W Queue Bypass - 16 x Bypass Max - 07 x 32 Byte Granularity - Disable(4 Bursts) vdimm set to 3.4v. should be able to memtest stable.
  8. when use X.5 multi, ur mem will be given a divider for free. so it is not advice to use a X.5 multi.
  9. hi vr-zoner, i try swapping also, result will be slightly better in some location, but still cant make the utt bh-5 to do 1T. they memtest stable at 245(ddr490) but at 240(ddr480) they already cant make 1T pass in any test in window.
  10. xinty

    compatible cooling

    thermalright xp120 should not b a problem. but the chipset HSF maybe cant.
  11. xinty

    Geil DDR600 2.5-4-4-7

    i think u cant get 4 x 512 at ddr600. try 2T?
  12. i havent try any other setting on tras, seen it is stable in memtest. i had sold my tccd base rams. so cant test them now. anyway i not eager to use my utt bh-5 on my nf4, but just hope can know the truth behind this stuff. super pi i also try before, only utt ch-5 can make a full pass on 32M, tccd also can at 1T, but not for utt bh-5. maybe my memcontrol love ch-5 or my skill is not there yet to play with rams.
  13. ya, utt run hot at high volatage. so i had put a fan when testing them. actually, i have try to do 1:1 for both utt at 240HTT. result still show only UTT ch-5 can pass OCCT. memtest for all the rams is error free. i also try to up vdimm to 3.5vdimm, memtest no error but still cant pass OCCT. 3120, auto, 4708 also had been try, still cant run OCCT. so, is it the mem-controller prefer UTT ch-5 better than utt bh-5?
  14. xinty

    Dram configuration

    most popular setting is 4708, 3102, 3072 and auto. i have gd luck at auto when using my UTT on a divider. 4708 seen like more stable at 300HTT on TCCD, this setting i follow those experience OCer.
  15. thanks for the reply. i have updated with more info. my question is why only UTT CH-5 can do 1T at above setting in my rig?
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