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OSKAR_WU

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Everything posted by OSKAR_WU

  1. Please update this firmware for PX-716A to solve the UDMA problem with SB450 south bridge ... http://oskarwu.myweb.hinet.net/716a_1029.zip
  2. Curretnly we found it's a common problem of ALL ATI SB450 problem ... We are seeking the help from ATI but no response yet ...
  3. Hello guys , could you please test if disable USB keyboard and mouse support can solve this problem ???
  4. Looks like a different situation from the result here , I will keep trying to duplicate the problem ... sorry for this problem ...
  5. With improved DDR 400 4 DIMM 1T capability ... DDR600 2T 4 TCCD is easy now as well ... Try to set driving setting level 9 + data drive level 4 ... dram voltage 2.92V ~ 3.00V ...
  6. I just got one board which may have the same problem as you guys even at all optimized and non overclocking setting ... If possible , try to leave the board along(still powered on) for a while when 4 LED is on and see what happened in the next ...
  7. I just got one board which may have the same problem as you guys even at all optimized and non overclocking setting ... If possible , try to leave the board along(still powered on) for a while when 4 LED is on and see what happened in the next ...
  8. Some guys complain about the system will have 4LED problem during bios exit but once it boot , it can boot into windows ... A reset can solve this problem ... If the board does not post , it's not the 4LED problem I refer here ...
  9. I need to collect you guy's bios setup to duplicate the problem ... First please download the tool http://oskarwu.myweb.hinet.net/RDX200/WinReload.rar Execute it under windows enviroment then 1 . Sellect Backup button 2 . Select Current 3 . Give it a file name ex : bioscurrentsetting.txt 4 . Reply with your detail hardware combination and attach this file for me to reload your problematic bios setting here ...
  10. 6/23 bios has been put as offical one and not beta anymore ... Generally , modify anything in bios that is voltage related need to be tested internally before it's released no matter it's alpha , beta or gamma ... Before the 7/04 beta bios , no voltage related code has been modified ... In order to solve that sometimes new DDR500 option will fail to boot in 7/02 beta bios , I change the protection I made before and it's a negligent fault of me ... I am in a rush of solving the 7/02 beta bios problem , I forget to do the complete testing about the modification I made because generally I did not set low " CPU VID " + high " CPU VID Special Control " in the same time and did not found the fatal bug I made ... In order to make every user happy , I have generate too much beta bios trying to satisfy every single user complain blah blah that this beta bios decrease my overclocking and please fix it and so on ... I don't really need to do all this and you can see this clearly when you have overclocking problem in other mb ... And something like this is impossible for any MB company ... I need to handle the complaint from other department because of this and this also affect which is the best version we should sent to do the validation and finally put it into official ... It's impossible for me to find a perfect one to satisfy everyone ... We have reset the validation for many times since 3/10 bios because some user compalin blah blah that my overclocking is not good with this one and fix it ... Finally we settle down 6/23 should be safe for general purpose and put it as official one now ... But there is still tons of complaint out there ... When you are trying to satisfy everybody , it's probably you will satisfy nobody ... Give me sometime ... The bug in 7/04 bios will be solved within this week with full verification in the change I made ... And I will modify the 5/10 based fix as well if you are not happy with 6/23 official one ...
  11. It's risk to use 7/04 bios if you want to use Low " CPU VID Control " & high " CPU VID Special Control " combination to generate the cpu voltage which may mislead you into thinking it's safe to use 123%,126%,133%,136% because you set " CPU VID " to a low voltage ...
  12. Generally , if anything related to voltage that may cause the damage to hardware , I would not put it into public beta and only release to certain people to test it first ... It's my fault to put 7/04 bios public beta ... The bug of 7/04 bios is this bios will program "CPU VID Special Control" first before setting protection to cpu voltage ... If you set "CPU VID" to a high voltage , EX : 1.55V then change to a low " CPU VID " and a high " CPU VID Special Control " in the same time , hit the save and exit ... Before the bios set the " CPU VID " to low voltage , the "CPU VID Special Control" will be programmed first without protection and may generate some core voltage like 1.55V * 1.36... Although it's a very short period , but If the cpu can not handle this voltage , the cpu will be dead ... Especially 90nm core cpu ... It's my fault and should blame me coz I have had done it :sad: ... I sincerely apologize for this mistake in beta bios before the change in 7/04 beta bios is fully verified ...
  13. """""" The bios may have chance to set wrong vcore voltage under certain circumstances ... """""""
  14. Due to the a mistake made in 7/04 beta bios , do not use 'Above VID * 123%' 'Above VID * 126%' 'Above VID * 133%' 'Above VID * 136%' option under "CPU VID Special Control" The bios may have chance to set wrong vcore voltage under certain circumstances ... If the cpu can not handle the wrong core voltage , it may be damaged ... This problem has only been found in 7/04 bios and 'Above VID * 123%' , 'Above VID * 126%' , 'Above VID * 133%' , 'Above VID * 136%' are used ... If you did not use the 4 settings , it will be ok you if still want to use 7/04 bios ... Please help me to remove this bios around the internet ... I apologize for the this mistake ...
  15. I got the board and memory today , there is a SMD capacitor on one of the dimms is broken ... I solder it back and test the two memory in my daily working FX-55 + dual channel platform ... One of the dimm(the one with broken smd capacitor) is damaged , it's not booting under dram voltage lower than 2.8V even at SPD timing and 200mhz fsb in single channel mode or dual channel mode ... After a certain period of rest(cool down) , sometimes it can boot @ 2.6V ... Most of the time it need 2.8V to boot ... The other one is complete ok ... 6/18 bios can help this situation if you set and save the dram voltage higher than 2.8V using the other good stick first and put the damaged one into the socket ... But the damaged stick perform exactly the same as the previous set I got , the damaged stick of previous set just need more boot up voltage than this set ... About the board you send , in order to use phase change cooler , the socket is filled with thermal grease ... I need to clean all of them before testing the board , this will takes some time ... I will post the motherboard result after I finish cleaning the socket ...
  16. 1 . 6/18 bios already implement DDR voltage programming before detecting dram during 1st power-on after AC off and on again ... If this bios does not solve the cold boot problem , it's very possible your dram is already in damaged status ... If I can not get the problematic setup to see if there is any workaround to solve it , I can not do anything more ... 2 . I send 2 working board out and I am still waiting the possible problematic board+dead utt memory combination(not cold boot combination) to come back ...
  17. 1 . You have a prejudice that it's the board generate voltage spike to kill the memory , I have say enough in previous post from what I know and the damaged componet I got ... Before I get more failure component to analysis , it's not a responsible action to comment more ... 2 . The cold boot issue may caused by two possible reason A . Ram damage due to over voltage , which makes it need high boot up voltage even at 200mhz no matter what the DRAM timing is (the board will only boot in 200mhz after AC off) B . The Ram need high voltage to boot in user select tight DRAM Timing even in 200mhz after AC off There is already a bios to verify if it's case B which will program DDR voltage to 3V(fixed at 3V) during DRAM detection sequence when 1st AC-on boot up) If it's case B , I will be responsible for this and solve it in future bios revision 3 . I know user is getting angry about this , but what do you think I can do before it's confirmed that the board generate spike voltage to kill the memory ? 4 . If you still think that the on board DRAM regulator may generate voltage spike and it's a fault design circuit , I must tell you any other voltage mod device won't be any better ... Lots of them are much worse than you can imaginate ... 5 . DFI(or any other MB company)will and must gurantee anything within the defined spec ... Anything out of guranteed spec , I and DFI will still be glad to help user to improve or solve it if I can see what's happened ... That's why there is a lot of beta bios trying to satisfy the user to overcome many kind of stange problem due to individual overclocking setup ... Is that what we must do just because we provide user the option to try any possibility they want ? Sorry , in my personal opinion , I really don't think so ... 6 . If there is a MB company provide 5.0V DRAM voltage and 1000mhz FSB in bios menu but which is not guranteed ... After I bought this board , I set the 5.0V DRAM voltage and 1000mhz FSB to see if it works ... But the system did not boot ... Two possible condition ... A . 1000 mhz fsb and 5.0V did generated but the setup I choose did not work or even cause the component to be damaged B . 1000 mhz fsb is not generated and the 5V is not generated Case A , the MB company already do what they should do Case B , the MB company need to be reponsible for the problem , at least they need to make 1000mhz fsb and 5.0V generated 7 . A simple question ... One MB that did not gurantee 3.3V DRAM voltage in spec(no matter the option is provided/supported or not) A voltage mod device from 3rd party company gurantee 3.3V DRAM power delivery(by their claim) 3.3V guranteed DRAM(by their claim) ... Put 3 of them together ... But the DRAM is dead finally , which product should be responsible for the DRAM death ?
  18. I am 99% confident that your DRAM is damaged just like the other ones ... SPD ROM on most of the current DIMM module can handle up to 5V voltage ... One of the two damaged stick I received start to act like what you encounter with your dram ... When I first got it , it can only boot in high voltage ... But after the memory is boot ok , lower down voltage to 2.6V @ SPD timing , it's stable and working good After some days of 3.2V torture testing(3.3V jumper location of course) , it still need high voltage to boot up , but now it requires 2.8V to work stable under SPD timing even at 200 mhz Now ... It need some rest(uncertain time period) to boot up again once the system power off even with high bootup voltage ...
  19. Sorry , but I did not know anything like what you said ... If you use 5V jumper to select the voltage higher than the DRAM or CPU can handle , either your CPU or DRAM will be damaged ... If the high voltage cause the current over the MOSFET limit , the DRAM regulator may be damaged ... But that number will be 53A continous when the MOSFET working under 100 degree Celcius , the peak current this MOSFET can handle is above 200A ... The MOSFET we use in DRAM power regulator is PHILIPS PHD78NQ03LT ... http://www.semiconductors.philips.com/acro...D78NQ03LT_4.pdf Anyway , all these are expected to happened when the board released ... We have put enough warning about all these thing ... Please be understand that the NF4 chipset is not power by DRAM voltage ... Also DFI or any other company will not gurantee or be responsible to anything damaged when you set voltage beyond the chip spec(cpu , dram , chipset , pci-e graphics or anything else ) ... I don't know what you hear from DFI SJ , but I never say anything like this to anyone in DFI SJ ...
  20. 1 . The 256k memory testing always runs no matter cold boot , warm boot , warm reset , or a cold reset ... 2 . The main reason the stick 1 I got can not boot @ 2.6V @ SPD timing is voltage , not the timing ... Which mean that I already try all kinds of Timing combination @ 2.6V , that 0000:0006h address still read back with wrong value ... The CMOS timing is already set within SPD timing detecting routine ... It's before the ram being tested ...
  21. I use stick 1 for example , this stick require very high voltage to be work @ boot I do a lot of try error and trace the bios , this is what I found ... 1 . SPD on it read the correct information as good stick 2 . The whole SPD memory detecting sequence is completed , I mean that the bios detect that there is memory presented in the memory bus , and complete setting all the timing parameter in K8 register 3 . After all that is completed , bios will start to do one thing first ... Check if the memory is able to pass the first 256K test of read/write , if it fail to do so , it will jump to the beep sequence , that's why you will hear BEEP , BEEP if there is no memory or the memory is bad ... Let me list some code example to show how this work After the SPD timing detection is completed , we will do something like this ========================================================= xor eax,eax xor dx,dx Next_64K_Test: mov es,dx ;segment to test cld ;fill the first 32Kb memory with specific pattern = eax = 00000000h mov cx,2000h ;32k to read pattern xor di,di rep stosd ;fill the second 32Kb memory with inversed pattern = eax = FFFFFFFFh not eax mov cx,2000H rep stosd ;Check the first 32Kb memory contents not eax ;get pattern to check mov cx,2000h ;32k memory to read xor di,di rep scasd jnz short Beep_Out ;error occured ;Do_next64k: ;Check the second 32Kb memory contents not eax ;get pattern to check mov cx,2000h ;32k memory to read rep scasd jnz short Beep_Out ;error occured add dh,10H ;next segment cmp dh,40H ;256K address ? jne short Next_64K_Test jmp short Ok_256K Beep_Out: ========================================================= We will fill in the first 32k memory of data pattern = 00000000h and fill in the second 32k memory of data pattern = FFFFFFFFh And read them back to check if the written data = data read back And loop 3rd , 4th .... 32K memory test until the first 256K is completely verified ok With the 1st stick which will fail to boot @ SPD timing @ 2.6V , it will fail in the 1st 32K memory read back test ... The first 32K memory fill code mov cx,2000h ;32k to read pattern xor di,di rep stosd will repeat to write dword data to the es:[di] address of memory to all 0 , in the first 32k memory fill in , es= 0 , di will range from 0 to cx*4 - 1 =2000h*4 - 1= 7FFFh = 32767 , 0~32767 = 32768 = 32K ... that means 0000:0000 ~ 0000:7FFFFh range of memory data will be written to all 0 ... The bios code will continue to fill the 2nd 32K memory from 0000:8000h to 0000:FFFFh to all 1 ... After that is completed , we will read back the first 32k data and check if they are all 0 ... With stick 1 , the 0000:0006h always return 04h but not 00h as expected , so the bios code will jump to BEEP loop and stop booting ... I guess there is one or two of the 16 chips in stick 1 is not working correctly @ 2.6V in the begining stage , let's why we write to all 0 to first 32K , but some bit is apparent read back as 1 ... That's all I found here , I think the damaged stick is not all that 16 chips are damaged , maybe only 1 bit in one or two of them does not work as expected in the SPD timing @ 2.6V ... This will cause that bios detect the DRAM is BAD , and stop booting ... Update : New finding about stick 1 condition ... after 1 days of 3.2V(using 3.3V jump) , 250mhz 2-2-5-2 burn in ... Stick 1 now require 2.8V to work complete stable under SPD timing(3-3-8-3) ... It start to become worse than I first got it ...
  22. I only need board + memory ... PM me the address I need to send you the board for exchange and what kind of MB model you have ...
  23. If you are confident that your board is the main reason that killed the dram , I can send you a board for exchange that I pre-test ok ... I can check if there is any uncommon situation in your board that may cause the problem ... I have many dram here ready to be tested if it will be killed easily ... :nod:
  24. 1 . 2 days is not totally impossible thing because you did not know what will happened if anything goes beyond the spec ... You can not compare a P2 CPU to a DRAM because their design and process is totally different ... 2 . I did not say that every single board will be problem free and it's impossible for 4V to kill the dram ... But from what I know with the stick & MB I got , I can only say something from what I see through my eyes ... 3 . We put the warning that using JP17 to raise the DRAM voltage range may kill the MB/DRAM/CPU from the beginning ... No matter what the problem comes from MB or DRAM or CPU , these are all expected to be happened ... Unless I can go and analysis every single case , it's hard to say the DRAM is damaged because of what kind of reason ...
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