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TSMC Announces Wafer-on-Wafer for Connecting Chips


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Last year AMD demonstrated the potential of combining components within dies and between dies to make powerful CPUs. With its Infinity Fabric, the distinct Zeppelin dies in the Threadripper and Epyc processors are able to work together, making 16 core/32 thread consumer products and 32 core/64 thread server products possible, and within the Zeppelin dies two Zen CCX modules are connected with the interconnect as well. These different components are all on the same plane though, so there is some distance between them, adding latency and increasing power requirements, but with a new capability of TSMC, we might see future products that combine dies and chips vertically.

Wafer on Wafer (WoW) is the new technology and it allows chips to be stacked on top of each other, and with through-silicon vias (TSVs) these chips can be directly connected. This means communications between the stacked chips will have much lower latency, and potentially very great bandwidth.

Stacking chips is not exactly a new idea as HBM, high bandwidth memory, is already an example of a stacked 2.5D design, but this WoW technology might enable more kinds of chips to be combined for dramatic impact. It will be interesting to see what comes of this, but sadly it is not possible to guess when we might see products launch using this technology.

Source: PCGamesN



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